tm
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TE
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T436432B
SDRAM
FEATURES
3.3V power supply
Clock cycle time : 5 / 5.5 / 6 / 7 / 8 / 10 ns
Internal four banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
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Burst Read Single-bit Write operation
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DQM for masking
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Auto refresh and self refresh
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64ms refresh period (4K cycle)
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MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length :
1 , 2 , 4 , 8 or full page for Sequential Burst
1 , 2 , 4 or 8 for Interleave Burst
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Available package type :
- 86 pin 400mil TSOP(II) and Lead free
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Operating temperature :
- 0 ~ +70
°C
2M x 32 SDRAM
512K x 32bit x 4Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T436432B is 67,108,864 bits synchronous
high data rate Dynamic RAM organized as
4 x 524,288 words by 32 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
PART NUMBER EXAMPLES
PART NO.
CLOCK
CYCLE TIME
5ns
5ns
5.5ns
5.5ns
6ns
6ns
7ns
7ns
8ns
8ns
10ns
10ns
MAX
FREQUENCY
PACKAGE
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
TSOP-II Lead free
TSOP-II
OPERATING
TEMPERATURE
T436432B-5SG
T436432B-5S
T436432B-55SG
T436432B-55S
T436432B-6SG
T436432B-6S
T436432B-7SG
T436432B-7S
T436432B-8SG
T436432B-8S
T436432B-10SG
T436432B-10S
200 MHz
200 MHz
183 MHz
183 MHz
166 MHz
166 MHz
143 MHz
143 MHz
125 MHz
125 MHz
100 MHz
100 MHz
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
0 ~ +70
°C
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
