tm
MD
S/C
TE
CH
FUNCTION
T66H0001A
SYMBOL
EIO
1
, EIO
2
Y
1
-Y
240
Mode selection pin
• When set to Vss level “L” , 8 bit parallel input mode is set.
• When set to V
DD
level “H” , 4 bit parallel input mode is set.
• Refer to “
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD
DRIVE OUTPUT PINS”
in Functional Operations.
Segment mode/common mode selection pin
• When set to V
DD
level “H” , segment mode is set.
Input/output pins for chip selection
• When L/R input is at Vss level “L” , EIO
1
is set for output , and EIO
2
is set for
input.
• When L/R input is at V
DD
level “H” , EIO
1
is set for input , and EIO
2
is set for
output.
• During output , set to “H” while LP·/XCK is “H” and after 240 bits of data have
been read , set to “L” for one cycle (from falling edge to falling edge of XCK),
after which it returns to “H”.
• During input , the chip is selected while EI is set to “L” after the LP signal is
input. The chip is non-selected after 240 bits of data have been read.
LCD drive output pins
• Corresponding directly to each bit of the data latch , one level (V
0 ,
V
12 ,
V
43 ,
or V
5
)
is selected and output.
• Table of truth values is shown in “TRUTH
TABLE”
in Functional Operations.
TM Technology Inc. reserves the right
P. 9
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision:A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
