XC61C
Series
■OPERATIONAL
EXPLANATION
(Especially prepared for CMOS output products)
①
When input voltage (V
IN
) rises above detect voltage (V
DF
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
②
When input voltage (V
IN
) falls below detect voltage (V
DF
), output voltage (V
OUT
) will be equal to the ground voltage
(V
SS
) level.
③
When input voltage (V
IN
) falls to a level below that of the minimum operating voltage (V
MIN
), output will become
unstable. In this condition, V
IN
will equal the pulled-up output (should output be pulled-up.)
④
When input voltage (V
IN
) rises above the ground voltage (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and detect release voltage (V
DR
) levels, the ground voltage (V
SS
)
level will be maintained.
⑤
When input voltage (V
IN
) rises above detect release voltage (V
DR
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
⑥
The difference between V
DR
and V
DF
represents the hysteresis range.
●Timing
Chart
5/17
TOREX [ TOREX SEMICONDUCTOR ]
