XC61F
Series
■OPERATIONAL
EXPLANATION
●CMOS
output
①
When a voltage higher than the release voltage (V
DR
) is applied to the voltage input pin (VI
N
), the voltage will
gradually fall. When a voltage higher than the detect voltage (V
DF
) is applied to VIN, output (V
OUT
) will be equal to the
input at V
IN
.
Note that high impedance exists at V
OUT
with the N-channel open drain configuration. If the pin is pulled up, V
OUT
will
be equal to the pull up voltage.
When V
IN
falls below V
DF
, V
OUT
will be equal to the ground voltage (V
SS
) level (detect state). Note that this also
applies to N-channel open drain configurations.
When VI
N
falls to a level below that of the minimum operating voltage (V
MIN
) output will become unstable. Because
the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage.
When V
IN
rises above the V
SS
level (excepting levels lower than minimum operating voltage), V
OUT
will be equal to
V
SS
until V
IN
reaches the V
DR
level.
Although V
IN
will rise to a level higher than V
DR
, V
OUT
maintains ground voltage level via the delay circuit.
Following transient delay time, V
IN
will be output at V
OUT
. Note that high impedance exists with the N-channel open
drain configuration and that voltage will be dependent on pull up.
②
③
④
⑤
⑥
Notes:
1. The difference between V
DR
and V
DF
represents the hysteresis range.
2. Release delay time (
t
DLY
) represents the time it takes for V
IN
to appear at V
OUT
once the said voltage has exceeded the
V
DR
level.
●Timing
Chart
(t
DLY
)
5/14
TOREX [ TOREX SEMICONDUCTOR ]
