TS3003
ELECTRICAL CHARACTERISTICS
V
DD
= 3V, V
PWM_CNTRL
= V
DD
, R
SET
= 4.32MΩ, R
LOAD(FOUT)
= Open Circuit, C
LOAD(FOUT)
= 0pF, C
LOAD(PWM)
= 0pF, C
PWM
= 47pF, unless otherwise
noted. Values are at T
A
= 25°C unless otherwise noted. See Note 1.
PARAMETER
Supply Voltage
Supply Current
SYMBOL
V
DD
I
DD
CONDITIONS
CPWM = V
DD
MIN
1.55
-40°C ≤ T
A
≤ 85°C
3.3
-40°C ≤ T
A
≤ 85°C
FOUT Period
FOUT Period Line
Regulation
FOUT Duty cycle
FOUT Period
Temperature
Coefficient
PWMOUT Duty Cycle
PWMOUT Duty Cycle
Line Regulation
C
PWM
Sourcing Current
UVLO Hysteresis
FOUT, PWMOUT
Rise Time
FOUT, PWMOUT
Fall Time
FOUT Jitter
RSET Pin Voltage
FDIV Input Current
Δt
FOUT
/ΔT
DC(PWMOUT)
ΔDC(PWMOUT)/V
I
CPWM
V
UVLO
t
RISE
t
FALL
(V
DD
=1.55V) – (V
DD
_
SHUTDOWN VOLTAGE
)
See Note 2, C
L
= 15pF
See Note 2, C
L
= 15pF
See Note 3
V(RSET)
I
FDIV
-40°C ≤ T
A
≤ 85°C
37
15
t
FOUT
Δt
FOUT
/V
1.55V ≤ V
DD
≤ 5.25V
49
0.02
41.6
-3
-40°C ≤ T
A
≤ 85°C
930
810
150
10
10
0.001
0.3
10
20
1050
1150
250
48
24
-40°C ≤ T
A
≤ 85°C
39
38
40.1
0.17
51
TYP
1.9
MAX
5.25
2.4
2.7
3.6
4.5
41.2
42
UNITS
V
µA
µs
%/V
%
%/°C
%
%
nA
mV
ns
ns
%
V
nA
V
PWM_CNTRL
= 0V
1.55V < V
DD
< 5.25V, FDIV2:0 = 000
Maximum Oscillator
Fosc
RSET= 330K
300
kHz
Frequency
High Level Output
Voltage, FOUT and
V
DD
- V
OH
I
OH
= 1mA
160
mV
PWMOUT
Low Level Output
Voltage, FOUT and
V
OL
I
OL
= 1mA
140
mV
PWMOUT
Dead Time
T
DT
FOUT edge falling and PWMOUT edge rising
106
ns
Note 1:
All devices are 100% production tested at T
A
= +25°C and are guaranteed by characterization for T
A
= T
MIN
to T
MAX
, as specified.
Note 2:
Output rise and fall times are measured between the 10% and 90% of the V
DD
power-supply voltage levels. The specification is based
on lab bench characterization and is not tested in production.
Note 3:
Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench
characterization and is not tested in production.
TS3003DS r1p0
Page 3
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
