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TS3005 参数 Datasheet PDF下载

TS3005图片预览
型号: TS3005
PDF下载: 下载PDF文件 查看货源
内容描述: 一个1.55V至5.25V , 1.35uA , 1.7ms至33hrs硅定时器 [A 1.55V to 5.25V, 1.35uA, 1.7ms to 33hrs Silicon Timer]
分类和应用:
文件页数/大小: 11 页 / 820 K
品牌: TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
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TS3005  
ELECTRICAL CHARACTERISTICS  
VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = 47pF, FDIV2:0 = 000 unless  
otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1.  
PARAMETER  
Supply Voltage  
SYMBOL  
CONDITIONS  
MIN  
1.55  
TYP  
1.35  
1.47  
20.5  
MAX  
5.25  
1.5  
1.9  
1.7  
2.1  
21.05  
21.5  
UNITS  
V
VDD  
CPWM = VDD  
-40°C TA 85°C  
-40°C TA 85°C  
Supply Current  
IDD  
µA  
ms  
19.95  
19.4  
FOUT Period  
tFOUT  
-40°C TA 85°C  
FOUT Period Line  
Regulation  
ΔtFOUT/V  
1.55V ≤ VDD 5.25V  
0.17  
0.02  
%/V  
%
FOUT Duty cycle  
49  
51  
FOUT Period  
Temperature  
Coefficient  
ΔtFOUT/ΔT  
%/°C  
0.08  
0.02  
0.12  
0.03  
PWMOUT Duty Cycle  
DC(PWMOUT)  
%
%
VPWM_CNTRL= 0V  
PWMOUT Duty Cycle  
Line Regulation  
ΔDC(PWMOUT)/V 1.55V < VDD < 5.25V, FDIV2:0 = 000  
-3  
930  
810  
1050  
1150  
FDIV2:0 = 000, 001  
ICPWM  
nA  
CPWM Sourcing Current  
-40°C ≤ TA ≤ 85°C  
FDIV2:0   000, 001  
97  
nA  
UVLO Hysteresis  
FOUT, PWMOUT  
Rise Time  
FOUT, PWMOUT  
Fall Time  
VUVLO  
tRISE  
(VDD=1.55V) (VDD  
_
)
150  
250  
mV  
SHUTDOWN VOLTAGE  
See Note 2, CL = 15pF  
10  
10  
ns  
ns  
tFALL  
See Note 2, CL = 15pF  
See Note 3  
FOUT Jitter  
0.001  
0.3  
%
V
RSET Pin Voltage  
V(RSET)  
IFDIV  
10  
20  
nA  
FDIV Input Current  
-40°C ≤ TA ≤ 85°C  
Maximum Oscillator  
Frequency  
High Level Output  
Voltage, FOUT and  
PWMOUT  
Fosc  
RSET= 360K  
IOH = 1mA  
586  
Hz  
VDD - VOH  
160  
mV  
Low Level Output  
Voltage, FOUT and  
PWMOUT  
VOL  
TDT  
IOL = 1mA  
140  
106  
mV  
ns  
Dead Time  
FOUT edge falling and PWMOUT edge rising  
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.  
Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based  
on lab bench characterization and is not tested in production.  
Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench  
characterization and is not tested in production.  
TS3005DS r1p0  
Page 3  
RTFDS