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TMC5031-LA 参数 Datasheet PDF下载

TMC5031-LA图片预览
型号: TMC5031-LA
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道,具有成本效益的控制器和驱动器可容纳两个2相双极步进电动机。 [Dual, cost-effective controller and driver for up to two 2-phase bipolar stepper motors.]
分类和应用: 驱动器控制器
文件页数/大小: 63 页 / 1662 K
品牌: TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
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TMC5031 DATASHEET (Rev. 1.07 / 2013-APR-30)
8
Pin
DIE_PAD
Number
-
Type
GND
Function
The exposed die attach pad is the thermal cooling pad for the IC
and shall be soldered to a ground pad, and be directly electrically
tied together with all GND pins. Use a large number of thermally
conducting vias to a PCB ground plane for best thermal and
electrical performance. The ground plane also acts as a heat
spreader to reduce thermal junction to ambient resistance.
Table 2.1 Low voltage digital and analog power supply pins
Pin
CPO
CPI
VCP
Number
35
36
37
Type
O(VCC)
I(VCP)
Function
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
Charge pump capacitor input: Provide external 22 nF / 50 V capacitor
to CPO.
Output of charge pump. Provide external 100 nF capacitor to VS.
Table 2.2 Charge pump pins
Pin
INT
PP
CSN
SCK
SDI
SDO
CLK
REFR2
REFL2
REFR1
REFL1
DRV_ENN
TST_MODE
-
Number
1
2
3
4
5
8
11
25
26
27
28
29
48
Type
O (Z)
O (Z)
I
I
I
O (Z)
I
I
I
I
I
I
I
Function
Tristate interrupt output based on ramp generator flags 4, 5, 6 & 7.
Tristate position compare output for motor 1 (poscmp_enable=1).
Chip select input of SPI interface
Serial clock input of SPI interface
Data input of SPI interface
Tristate data output of SPI interface (enabled with CSN=0)
Clock input for all internal operations. Tie low to use internal
oscillator. A high signal disables the internal oscillator until power
down.
Right reference switch input for motor 2
Left reference switch input for motor 2
Right reference switch input for motor 1
Left reference switch input for motor 1
Enable (not) input for drivers (tie to GND). Switches off all motor
outputs (set high for disable).
Test mode input. Puts IC into test mode. Tie to GND for normal
operation.
Unused pins – no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
13, 23, 38 N.C.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)
www.trinamic.com