T
R
I
Q
U
I
N
T
S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
FBIN
11
TQ1090
S1
10
REFCLK S0
9
8
GND
7
GND
6
GND
5
TEST
12
VDD
13
Phase
Detector
VCO
4
VDD
3
2
Q10
Q9
11-Output
Configurable
Clock Buffer
Features
Q0
14
GND
15
Q1
Q2
16
17
MUX
Divide Logic
÷2
Output Buffers Group C
Group A
Group B
1
GND
28
27
S1 S0
Q8
Q7
VDD
18
26
VDD
• Wide frequency range:
33 MHz to 45 MHz
65 MHz to 90 MHz and
130 MHz to 180 MHz
• Output configurations:
four outputs at f
REF
four outputs at 2x f
REF
two output at 4x f
REF
or
five outputs at
1
/
2
x f
REF
three outputs at f
REF
two outputs at 2x f
REF
• Selectable Phase Shift:
–2t, –t, 0, +t (t = 1/f
vco
)
• Low output-to-output skew:
150 ps (max) within a group
• Near-zero propagation delay
–350 ps
±
500 ps (max) or
–350 ps
±
700 ps (max)
• TTL-compatible I/O with 30 mA
output drive
• Ideal for Power PC
™
designs
• 28-pin J-lead surface-mount
package
SYSTEM TIMING
PRODUCTS
19
20
21
22
23
24
25
GND
Q3
Q4
VDD
Q5
Q6
GND
TriQuint’s TQ1090 is a configurable clock buffer which generates 11
outputs, operating over a wide range of frequencies from 33 MHz to
45MHz, 65 MHz to 90 MHz and 130 MHz to 180 MHz. The outputs are
available at 1x, 2x and 4x, or at
1
/
2
x, 1x and 2x, or at
1
/
4
x,
1
/
2
x and
1x the reference clock frequency, f
REF
.
When one of the Group A outputs (Q0–Q4) is used as feedback to the PLL,
all Group A outputs will be at f
REF
, all Group B outputs (Q5–Q8) will be at
2x f
REF
and all Group C outputs (Q9,Q10) will be at 4x f
REF
. When one of the
Group B outputs is used as feedback to the PLL, all Group A outputs will
be at
1
/
2
x f
REF
, all Group B outputs will be at f
REF
and all Group C outputs
will be at 2x f
REF
. When one of the Group C outputs is used as feedback to
the PLL, all Group A outputs will be at
1
/
4
x f
REF
, all Group B outputs will be
at
1
/
2
x f
REF
and all Group C outputs will be at f
REF
.
A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation.
This completely self-contained PLL requires no external capacitors or
resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a frequency
range from 260 MHz to 360 MHz. By feeding back one of the output clocks
to FBIN, the PLL continuously maintains frequency and phase synchron-
ization between the reference clock (REFCLK) and each of the outputs.
For additional information and latest specifications, see our website:
www.triquint.com
1
TRIQUINT [ TRIQUINT SEMICONDUCTOR ]
