TQ3632
Data Sheet
TQ3632 Product Description
The TQ3632 LNA uses a cascode low noise amplifier along with
signal path switching. A bias control circuit sets the quiescent
current for each mode and ensures peak performance over
process and temperature, see Figure 1. In the application,
CMOS level signals are applied to pins 1 and 5 and are
decoded by an internal logic circuit, this sets the device to the
desired mode. See Table 1 for truth table.
In the high gain mode, switches S1, S2, and S5 are closed, with
switches S3 and S4 open. In the bypass mode, switches S1,
S2, and S5 are open, with switches S3 and S4 closed. Six
internal switches ensures there are no parasitic feedback paths
for the RF signal. In the AMPS mode, control logic switches the
LNA into a low current bias condition.
Only three external components are needed. The chip uses an
external cap and inductor for the input match to pin 3. The
output is internally matched to 50 ohms at pin 6. A Vdd bypass
cap is required close to pin 8.
External degeneration of the cascode is required between pin 4
and ground. However, a small amount of PC board trace can
be used as the inductor. Alternatively, if an extra component
can be tolerated, a small value chip inductor could be used.
See Figure 2.
VDD
Operation
MODE
High Gain
C2
0
1
High Gain
Low linearity
Bypass
1
1
-2(dB)
0
C3
0
0
1
11(dB)
Typical Gain
13(dB)
Table 1 LNA States and Control Bits
LNA Input Network Design
Input network design for most LNA’s is a straightforward
compromise between noise figure and gain. The TQ3632 is no
exception, even though it has 3 different modes. The device
was designed so that one only needs to optimize the input
match in the high gain mode. As long as the proper grounding
and source inductance are used, the other two modes will
perform well with the same match.
It is probably wise to synthesize the matching network
component values for some intermediate range of Gamma
values, and then by experimentation, find the one which
provides the best compromise between noise figure and gain.
The quality of the chip ground will have some effect on the
match, which is why some experimentation will likely be needed.
The input match will affect the output match to some degree, so
S22 should be monitored.
The values used on our evaluation board may be used as a
starting point.
Control
Logic C2
VDD
R1
8
1
Bias and Switch Control Logic
C7
2
GND
7
GND
LNA IN
L1
S6
3
S1
6
S2
LNA OUT
Noise Parameter Analysis
A noise parameter analysis is shown on the next page for the
high gain and high gain low linearity modes. A “nominal” device
was mounted directly on a standard evaluation board without a
matching network (thru connected). The input reference plane
was set at pin 3 and board loss was included in the calculations.
C7 was set to 4.7pF.
RFIN
RF
OUT
C8
4
Lbrd
DC
GND
S3
S5
S4
5
Control
Logic C3
Figure 1 TQ3632 Simplified Schematic
6
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