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S E M I C O N D U C T O R, I N C .
SONET/SDH
Overhead
Processor
TQ8105
or
TQ8106
SONET/SDH
Transceiver
Rx O/E
with
CDR
Tx O/E
TQ8105/8106
PRELIMINARY DATA SHEET
TELECOM
PRODUCTS
Reference
Clock
SONET/SDH
Transceivers
Features
SONET/SDH
Overhead
Processor
TQ8106
SONET/SDH
Transceiver
with CDR
Rx O/E
Tx O/E
• Single-chip, byte-wide Mux,
Demux, Framer, and Tx clock-
synthesis PLL with enhanced
diagnostics
• TQ8106 includes monolithic
Clock and Data Recovery
• SONET/SDH/ATM compliant for
STS-12/STM-4 (622 Mb/s) or
STS-3/STM-1 (155 Mb/s) rates
• 155.52, 77.76, 51.84, 38.88, or
19.44 MHz reference clock inputs
with TTL, PECL, or ECL level
• 38.88 MHz and 51.84 MHz clock
outputs for UTOPIA as well as
byte clock rate (77.76 or 19.44 MHz)
• External RC-based loop filters
• Integrated loopbacks with
enhanced line and reference
clock diagnostics
• Direct-coupled standard, PECL,
high-speed I/O with ECL option
• Clean TTL interface to
PMC-Sierra devices
• 100-pin 14x14 mm JEDEC
plastic package
• +5V-only supply for PECL I/O
(–5.2V required for ECL I/O option)
• –40 to +125
°
C case operating
temperature
The TQ8105/TQ8106 are SONET/SDH transceivers that integrate
multiplexing, demultiplexing, SONET/SDH framing, clock-synthesis PLL, and
enhanced line and clock diagnostic functions into a single monolithic device.
The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a
Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow
maximum flexibility in the selection of internal/external Clock and Data
Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources.
On-chip PLLs use external RC-based loop filters to allow custom tailoring of
loop response and support the wide range of reference clock frequencies
found in SONET/SDH/ATM systems. For transmit clock synthesis or for CDR,
the PLLs exceed ANSI, Bellcore, and ITU jitter specifications for systems
when combined with industry-typical O/E devices such as Sumitomo, AT&T,
HP, and AMP. The TQ8105/TQ8106 PLLs provide byte clocks and constant-
rate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing
clocking for UTOPIA and other system busses. Transmit data may also be
clocked into the devices with respect to the reference clock.
Operating from a single +5V supply, the TQ8105/TQ8106 provides fully
compliant functionality and performance, utilizing direct-connected PECL
levels (differential or single-ended) for high-speed I/O. As compared to AC-
coupled schemes, the direct-coupled connections reduce jitter and
switching-level offsets due to data patterns. The TQ8105/TQ8106 can also
provide direct connection to high-speed I/O utilizing ECL levels with a –5V
supply. Low-speed bus, control, and clock I/O utilize TTL levels. (An ECL/
PECL reference clock input is also provided; at 155.52 MHz the input should
be only PECL/ECL.) Output TTL pins can be tristated and may also be
configured for V
OH
with a 3.3V supply connection.
For additional information and latest specifications, see our website:
www.triquint.com
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TRIQUINT [ TRIQUINT SEMICONDUCTOR ]
