PA4867
PIN CONFIGURATION
CMOS IC
PIN DESCRIPTION
PIN NO.
1
2, 7, 19
3
4, 17
5
6
8
9
10
11
12
13
14
15
16
18
20
PIN NAME
SHUTDOWN
GND
+OUTA
V
DD
-OUTA
-INA
+INA
-INA
2
MUX CTRL
-INB
2
NC
+INB
BYPASS
-INB
-OUTB
+OUTB
HP-IN
I/O
I
O
O
I
I
I
I
I
I
O
O
I
PIN DESCRIPTION
Entire IC into the shutdown mode when this pin connected to the V
DD
Ground
Channel A + output in BTL mode, high impedance in SE mode
Supply voltage
Channel A - output in BTL mode, + output in SE mode
Inverting input of channel A
Non-inverting input of channel A, connected to BYPASS pin inside the IC
Inverting input of channel A
2
Inverting input of channel B
2
No Connection
Non-inverting input of channel B, connected to BYPASS pin inside the IC
Internal mid-supply bias reference bypassing
Inverting input of channel B
Channel B - output in BTL mode, + output in SE mode
Channel B + output in BTL mode, high impedance in SE mode
Output mode select, connected to the V
DD
for SE mode or GND for BTL mode
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
2 of 7
QW-R502-125.A
UMC [ UMC CORPORATION ]
