US3010/3010A
Application Information
An example of how to calculate the components for the
application circuit is given below.
Assuming, two sets of output conditions that this regu-
lator must meet,
a) Vo=2.8V , Io=14.2A,
∆Vo=185mV, ∆Io=14.2A
b) Vo=2V , Io=14.2A,
∆Vo=140mV, ∆Io=14.2A
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total
∆Vo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as :
ESR
≤
100
=
7 mΩ
14.2
The Sanyo M V G X seres i a good choi t achi
i s
ce o
eve
bot t prce and per or ance goal The 6M V1500G X
h he i
f m
s.
, 1500uF, 6. has an E S R of l
3V
ess t
han 36 m
Ω
typ .
Selecting 6 of these capacitors in parallel has an ESR
of
≈6
mΩ which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic “FA” series or
the Nichicon “PL” series.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly
reduce the number
of output capacitors, by level shifting the DC regu-
lation point when transitioninig from light load to
full load and vice versa.
To accomplish this, the out-
put of the regulator is typically set about half the DC
drop that results from light load to full load. For example,
if the total resistance from the output capacitors to the
Slot 1 and back to the GND pin of the device is 5mΩ and
if the total
∆I,
the change from light load to full load is
14A, then the output voltage measured at the top of the
resistor divider which is also connected to the output
capacitors in this case, must be set at half of the 70 mV
or 35mV higher than the DAC voltage setting.
This intentional voltage level shifting during the load tran-
sient eases the requirement for the output capacitor ESR
at the cost of load regulation. One can show that the
new ESR requirement eases up by
half the total trace
resistance.
For example, if the ESR requirement of the
output capacitors without voltage level shifting must be
7mΩ then after level shifting the new ESR will only need
to be 8.5mΩ if the trace resistance is 5mΩ (7+5/2=9.5).
However, one must be careful that the combined “volt-
age level shifting” and the transient response is still within
the maximum tolerance of the Intel specification. To in-
sure this, the maximum trace resistance must be less
than:
Rs≤ 2(Vspec - 0.02*Vo -
∆Vo)/∆I
Where :
Rs=Total maximum trace resistance allowed
Vspec=Intel total voltage spec
Vo=Output voltage
∆Vo=Output
ripple voltage
∆I=load
current step
For example, assuming:
Vspec=±140 mV=±0.1V for 2V output
Vo=2V
∆Vo=assume
10mV=0.01V
∆I=14.2A
Then the Rs is calculated to be:
Rs≤ 2(0.140 - 0.02*2 - 0.01)/14.2=12.6mΩ
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6 mΩ , the power dissipated is
(Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to
be dissipated in a system. So, if the Rs=5mΩ, then the
power dissipated is about 1W which is much more ac-
ceptable. If level shifting is not implemented, then the
maximum output capacitor ESR was shown previously
to be 7mΩ which translated to
≈
6 of the 1500uF,
6MV1500GX type Sanyo capacitors. With Rs=5mΩ, the
maximum ESR becomes 9.5mΩ which is equivalent to
≈
4 caps. Another important consideration is that
if a
trace is being used to implement the resistor, the
power dissipated by the trace increases the case
temperature of the output capacitors which could
seriously effect the life time of the output capaci-
tors.
Output Inductor Selection
The output inductance must be selected such that un-
der low line and the maximum output voltage condition,
the inductor current slope times the output capacitor
ESR is ramping up faster than the capacitor voltage is
4-8
Rev. 1.1
5/18/98
UNISEM [ UNISEM ]
