VL-FS-MDLS161615SP-02 REV. A
(MDLS161615SP-LV-G-LED04G (BB))
DEC/2004
PAGE 9 OF 13
5.2 Timing Specifications
At Ta = 0
°C
To +50
°C,
VDD = +5V±5%, GND = 0V.
Refer to Fig. 2, the bus timing diagram for write mode.
Table 6
Parameter
Enable cycle time
Enable “High” level pulse width
Enable rise time
Enable fall time
RS, R/W set-up time
RS, R/W address hold time
Data output delay
Data hold time
Symbol
t
CYCE
t
WHE
t
RE
t
FE
t
AS
t
AH
t
DS
t
DHR
Min.
500
300
-
-
60
100
10
100
10
Max.
-
-
25
25
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
8-bit operation mode
4-bit operation mode
Refer to Fig. 3, the bus timing diagram for read mode.
Table 7
Parameter
Enable cycle time
Enable “High” level pulse width
Enable rise time
Enable fall time
RS, R/W set-up time
RS, R/W address hold time
Read data output delay
Read data hold time
Symbol
t
CYCE
t
WHE
t
RE
t
FE
t
AS
t
AH
t
RD
t
DHR
Min.
500
300
-
-
60
100
10
-
20
Max.
-
-
25
25
-
-
-
190
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
8-bit operation mode
4-bit operation mode
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