CD-700, VCXO Based PLL
Layout Considerations
To achieve stable, low noise performance good analog layout techniques should be incorporated and a
partial list is shown below.
The CD-700 should be treated more like an analog device and the power supply must be well decoupled
with a good quality RF 0.01 uF capacitor in parallel with a 0.1 uF capacitor, located as close to pin 14 as
possible and connected to ground. In some cases, a
Π
filter such as a large capacitor (10uF) to ground, a
series ferrite bead or inductor with 0.01 uF and 100 pF capacitor to ground to decouple the device
supply.
The traces for the OUT1, OUT2, RCLK and RDATA ouputs should be kept as short as possible. It is
common practice to use a series resistor ( 50 to 100 ohms ) in order to reduce reflections if these traces
are more than a couple of inches long. Also OUT1, OUT2, RCLK and RDATA should not be routed
directly underneath the device.
The op-amp loop filter components should be kept as close to the device as possible and the feedback
capacitor should be located close to the op-amp input terminal. The loop filter capacitor(s) should be low
leakage (polarized capacitors are allowed).
Unused outputs should be left floating and it is not required to load or terminate them (such as an ECL or
PECL output). Loading unused outputs will only increase current consumption.
Application Circuits
10k 0.01uF 10k 2.2uF 330k 20k
0.1uF
pin 3
8 kHz
(pin 5)
pin 2
pin 1
pin 16
pin 13
VCXO
∅
44.736 MHz
÷
CD-700
pin 15
3.3 V
16kHz (pin 6)
10k
10k , 2.2uF
÷
2796
Figure 8. 8kHz to 44.736 MHz Frequency Translation
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Page 9 of 14
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev : 06Apr08
VECTRON [ Vectron International, Inc ]
