CD-700, VCXO Based PLL
Performance Characteristics
Table 1. Electrical Performance
Parameter
Output Frequency (ordering
option)
OUT1, 5.0 V option
OUT1, 3.3 V option
Supply Voltage
1
+5.0
+3.3
Supply Current
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Transition Times
Rise Time
2
Fall Time
2
Input Logic Levels
Output Logic High
2
Output Logic Low
2
Loss of Signal Indication
Output Logic High
2
Output Logic Low
2
Nominal Frequency on Loss of Signal
Output 1
Output 2
Symmetry or Duty Cycle
3
Out 1
Out 2
RCLK
Absolute Pull Range (ordering
option)
over operating temperature, aging, and
power supply variations
Symbol
Min
1.000
1.000
Typical
Maximum
77.760
77.760
Units
MHz
MHz
V
V
mA
V
V
ns
ns
V
V
V
V
ppm
ppm
%
%
%
ppm
V
DD
4.5
2.97
I
DD
V
OH
V
OL
t
R
t
F
V
IH
V
IL
V
OH
V
OL
2.0
0.5
2.5
0.5
±75
±75
SYM1
SYM2
RCLK
APR
40/60
45/55
40/60
±50
±80
±100
0.5
0.3
Positive
0.53
0.35
0/70 or –40/85
I
VCXO
±1
rad/V
rad/V
°C
uA
2.5
0.5
5
5
5.0
3.3
5.5
3.63
63
Test Conditions for APR (+5.0 V option)
Test Conditions for APR (+3.3 V option)
Gain Transfer
Phase Detector Gain
+5V option
+3.3V option
Operating temperature (ordering
option)
Control Voltage Leakage Current
V
C
V
C
4.5
3.0
V
V
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which
these parameters are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
t
R
80
%
t
F
I
DD
14
V
DD
+
-
13
7
15pF
650Ω
1.4V
20
%
.
1μF
.01μF
I
C
V
C
16
+
-
On Time
Period
1.8k
Figure 2. Output Waveform
Vectron International 166 Glover Avenue, Norwalk CT 06856-5160
Figure 3. OUT1, OUT2, RCLK, RDATA
Tel:1-88-VECTRON-1
e-mail: vectron@vectron.com
VECTRON [ Vectron International, Inc ]
