VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7124
Features
• ANSI X3T11 Fibre Channel Compliant at 1.0625Gb/s
• IEEE 802.3z Gigabit Ethernet Compliant at 1.25Gb/s
• Five Port Bypass Circuits (PBCs)
• On-Chip Transmit Termination
Quad Port Bypass Circuit
• 3.3V, 0.25W Typical Power
• 0.35um CMOS, a Velocity Family Member
• 44-Pin, 10mm PQFP Package
General Description
The VSC7124 contains five cascaded Port Bypass Circuits (PBCs) used to steer serial signals. This part is typ-
ically used in distributing Fibre Channel signals to an array of disk drives in an FC-AL loop as illustrated in Fig-
ure 1. The VSC7124 can be used with any of the Vitesse JBOD circuits to implement FC-AL JBODs of
virtually any size. In Figure 1, the first VSC7127’s CRU is configured as a Repeater to attenuate jitter. The
VSC7124 does not contain a CRU in order to reduce power and cost. The second VSC7127’s CRU is config-
ured as a retimer so that the output of the device is a jitter compliance point.
Each PBC is a multiplexer that is controlled by the corresponding SELx line which, if HIGH, selects the exter-
nal input or, if LOW, selects the output of the previous PBC.
VSC7124 Block Diagram
O1+
O1-
I1+
I1-
SEL1
O2+
O2-
I2+
I2-
SEL2
O3+
O3-
I3+
I3-
SEL3
O4+
O4-
I4+
I4-
SEL4
O0+
O0-
I0+
I0-
SEL0
1
0
1
0
1
0
1
0
1
0
PBC1
PBC2
PBC3
PBC4
PBC0
G52293-0, Rev 2.3
05/07/01
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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