VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Figure 4: REFCLK Timing Waveforms *
REFCLK
V
IH(MIN)
V
IL(MAX)
NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state.
Table 2: Reference Clock Requirements
Parameters
FR
FO
DC
T
R
, T
F
Description
Frequency Range
Frequency Offset
Duty Cycle
Rise and Fall Time
Min
105
-200
35
Typ
Max
107
200
65
2.0
Units
MHz
ppm
%
ns
Conditions
Maximum frequency offset
between transmit and receive
reference clocks on one link
Measured at 1.5V
Between V
IL(MAX)
and V
IH(MIN)
DC Characteristics
(Over recommended operating conditions)
Parameters
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
∆V
OUT75(1)
∆V
OUT50(1)
∆V
IN(1)
V
DD
P
D
I
DD
I
DDA
Description
Output HIGH voltage (TTL)
Output LOW voltage (TTL)
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH current (TTL)
Input LOW current (TTL)
TX output differential peak-to-
peak voltage swing
TX output differential peak-to-
peak voltage swing
Receiver differential peak-to-peak
input Sensitivity RX
Supply voltage
Power dissipation
Current (all supplies)
Current (V
DDA
)
Min
2.4
Typ
Max
0.5
Units
V
V
V
V
µA
µA
mVp-p
mVp-p
mVp-p
V
mW
mA
mA
Conditions
I
OH
= -1.0mA
I
OL
= +1.0mA
2.0
0
50
5.5
0.8
500
-500
V
IN
=2.4V
V
IN
=0.5V
75Ω to V
DD
– 2.0 V
50Ω to V
DD
– 2.0 V
Internally biased to V
DD
/2
3.3V±5%
Outputs open, V
DD
= V
DD
max.
±2%
Outputs open, V
DD
= V
DD
max
V
DDA
= V
DD
max
1200
1000
400
3.14
707
215
50
2200
2200
2600
3.47
902
260
70
NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements.
Page 6
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52298-0, Rev 4.3
05/01/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
