VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
Features
• 802.3z Gigabit Ethernet Compliant 1.25
Gb/s Transceiver
• ANSI X3T11 Fibre Channel Compliant
1.0625 Gb/s Transceiver
• 0.98 to 1.36 Gb/s Full Duplex Operation
• 10 Bit TTL Interface for Transmit and
Receive Data
10-bit Transceiver for Fibre
Channel and Gigabit Ethernet
• TTL or PECL Reference Clock
• Automatic Lock-to-Reference
• RX Cable Equalization and Signal Detect
• JTAG Access Port for Testability
• 64-pin, 10mm PQFP Packaging
• Single +3.3V Supply, 650 mW
General Description
The VSC7133 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
pinouts. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of the TTL/PECL REF-
CLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK fre-
quency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit,
deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty clocks. The
VSC7133 receiver detects “Comma” characters for frame alignment. An analog/digital signal detection circuit
indicates that a valid signal is present on the RX input. A cable equalizer compensates for Inter Symbol Interfer-
ence in order to increase maximum cable distances. The VSC7133 contains PLL circuitry for synthesis of the
baud-rate transmit clock, and extraction of the clock from the received serial stream. The VSC7133 is similar to
the VSC7123 but has either a TTL or a PECL reference clock.
VSC7133 Block Diagram
R(0:9)
10
QD
Serial to
Q Parallel D
÷10
QD
2:1
RX+
RX-
RCLK
RCLKN
COMDET
ENCDET
EWRAP
SIGDET
T(0:9)
REFCLKP
REFCLKN
10
Clock
Recovery
÷20
Comma
Detect
Signal
Detect
Parallel
to Serial
DQ
DQ
TX+
TX-
x10 Clock
Multiply
NOT SHOWN: JTAG Boundary Scan
G52187-0 Rev. 2.4
1/17/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
