ESE
VITESSE
SEMICONDUCTOR
CORPORATION
SEMICONDUCTOR
CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
A similar situation exists when TBC is used to define a data eye; only the rising edges of TBC are used to
define the external data timing. The internal clock active edges are placed at 90× and 270× points between
consecutive TBC rising edges (which are assumed to be 360× apart).
Figure 2: Transmit Timing,
TMODE(2:0)
= 000
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
T(7:0)
C/D
WSEN
Valid
Valid
Valid
Figure 3: Transmit Timing,
TMODE(2:0)
= 10X
TBC
T(7:0)
C/D
WSEN
Valid
Valid
Valid
Figure 4: Transmit Timing,
TMODE(2:0)
= 11X (“ASIC-Friendly” Timing)
0
o
90
o
180
o
270
o
360
o
TBC
T(7:0)
C/D
WSEN
Valid
Valid
Valid
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01
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