VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Features
• 4 ANSI X3T11 Fibre Channel and IEEE
802.3z Gigabit Ethernet Compliant Trans-
ceivers
• Over 8 Gb/s Duplex Raw Data Rate
• Redundant PECL Tx Outputs and Rx Inputs
• 8B/10B Encoder/Decoder per Channel,
Optional Encoder/Decoder Bypass Operation
• “ASIC-Friendly
TM
” Timing Options for
Transmitter Parallel Input Data
• Elastic Buffers for Intra/Inter-Chip Cable
Deskewing and Channel-to-Channel Align-
ment
• Tx/Rx Rate Matching via IDLE Insertion/
Deletion
Multi-Gigabit Interconnect Chip
• Compatible with VSC7211/7212/7214
• Fast-Locking CRU: 100-Bit Clock Periods
• Received Data Aligned to Local REFCLK or to
Recovered Clock
• PECL Rx Signal Detect and Cable Equalization
• Per-Channel Serial Tx-to-Rx and Parallel Rx-to-
Tx Internal Loopback Modes
• Clock Multiplier Generates Baud Rate Clock
• Automatic Lock-to-Reference
• JTAG Boundary Scan Support for TTL I/O
• Built-In Self Test
• 3.3V Supply, 3.0W Typ, 3.5W Max.
• 256-pin, 27mm BGA Package
VSC7217 Block Diagram
TRANSMITTER
PTXEND
TD(7:0)
C/DD
WSEND
RECEIVER
LBTXD
PTXD+
PTXD-
RTXD+
RTXD-
LBEND(1:0)
RXP/RD
PRXD+
PRXD-
RRXD+
RRXD-
LBENC(1:0)
RXP/RC
PRXC+
PRXC-
RRXC+
RRXC-
LBENB(1:0)
RXP/RB
PRXB+
PRXB-
RRXB+
RRXB-
LBENA(1:0)
RXP/RA
PRXA+
PRXA-
RRXA+
RRXA-
8
D Q
8
8B/10B
10
Encode
RTXEND
PTXENC
Clk/Data
Recovery
PSDETD
RSDETD
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RD(7:0)
IDLED
KCHD
ERRD
RCLKD
RCLKDN
TC(7:0)
C/DC
WSENC
8
D Q
8
LBTXC
PTXC+
PTXC-
RTXC+
RTXC-
8B/10B
10
Encode
RTXENC
PTXENB
Clk/Data
Recovery
PSDETC
RSDETC
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RC7:0)
IDLEC
KCHC
ERRC
RCLKC
RCLKCN
TB(7:0)
C/DB
WSENB
8
D Q
8
LBTXB
PTXB+
PTXB-
RTXB+
RTXB-
8B/10B
10
Encode
RTXENB
PTXENA
Clk/Data
Recovery
PSDETB
RSDETB
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RB(7:0)
IDLEB
KCHB
ERRB
RCLKB
RCLKBN
TA(7:0)
C/DA
WSENA
KCHAR
8
D Q
8
LBTXA
PTXA+
PTXA-
RTXA+
RTXA-
8B/10B
10
Encode
4
RTXENA
Clk/Data
Recovery
PSDETA
RSDETA
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RA(7:0)
IDLEA
KCHA
ERRD
RCLKA
RCLKAN
WSI
FLOCK
Channel
Align
WSO
TBCA
TBCB
TBCC
TBCD
DUAL
REFCLKP
REFCLKN
Tx Clock
x20/x10
Clock Gen
CAP0 CAP1
REFCLK
TBERRA
TBERRB
TBERRC
TBERRD
TMODE(2:0)
RMODE(1:0)
RESETN
ENDEC
BIST
TRSTN
TMS
TDI
TCK
JTAG
Boundary
Scan
TDO
G52325-0, Rev. 3.0
6/14/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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