VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8114
Features
•
Operates at STS-12/STM-4 (622.08Mb/s)
Data Rate
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
• Loss of Signal (LOS) Input & LOS Detection
• +3.3V/5V Programmable PECL Serial Interface
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Mode
• Provide PECL Reference Clock Inputs
• Meets Bellcore, ITU and ANSI Specifications
for Jitter Performance
• Low Power - 0.9Watts Typical
• 100 PQFP Package
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 622.08MHz
High Speed Clock (Mux)
• On Chip Clock Recovery of the 622.08MHz
High Speed Clock (Demux)
• 8-Bit Parallel TTL Interface with Parity Error
Detection and Generation
• SONET/SDH Frame Recovery
General Description
The VSC8114 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication
Unit (PLL) for high speed clock generation as well as a Clock and data Recovery Unit (CRU) with 8-bit serial-
to-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direc-
tion (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-
ment loopback modes and a loop time mode. The part is packaged in a 100PQFP with an integrated heat
spreader for optimum thermal performance and reduced cost. The VSC8114 provides an integrated solution for
ATM physical layers and SONET/SDH systems applications.
Functional Description
The VSC8114 is designed to provide a SONET/SDH compliant interface between the high speed optical
networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8114
converts 8 bit parallel data at 77.76Mb/s to a serial bit stream at 622.08Mb/s. The device also provides a Facility
Loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly
to the high speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to gen-
erate the high speed clock for the serial output data stream from input reference frequencies of 19.44 or 77.76
MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode, thus synchronizing
the entire part to a single clock. The block diagram on page 2 shows the major functional blocks associated with
the VSC8114.
The receive section provides the serial-to-parallel conversion, converting 622Mb/s bit stream to an 8 bit par-
allel output at 77.76MHz. A Clock Recovery Unit (CRU) is integrated into the receive circuit to recover the high
speed clock from the received serial data stream. The receive section provides an Equipment Loopback function
which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel out-
puts. The VSC8114 also provides the option of selecting between either its internal CRU’s clock and data sig-
nals, or optics containing a CRU clock and data signals. The receive section also contains a SONET/SDH frame
G52185-0, Rev 4.0
11/1/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
