VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8117
Features
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
•
Operates at Either STS-3/STM-1 (155.52Mb/s)
or STS-12/STM-4 (622.08Mb/s) Data Rates
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the
155.52MHz
or
622.08MHz High Speed Clock (Mux)
• On Chip Clock Recovery of the
155.52MHz or
622.08MHz High Speed Clock (Demux)
• 8 Bit Parallel TTL Interface
• SONET/SDH Frame Recovery
• Loss of Signal (LOS) Input & LOS Detection
• +3.3V/5V programmable PECL Serial Interface
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Mode
• Provides TTL and PECL reference clock inputs
• Meets Bellcore, ITU and ANSI Specifications for
Jitter Performance
• Low Power - 1.0 Watts Typical
• 64 PQFP Package
General Description
The VSC8117 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication
Unit (PLL) for the high speed clock as well as a clock and data recovery unit (CRU) with 8 bit serial-to-parallel
and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux).
The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains
SONET/SDH frame detection and recovery. The device provides facility loopback, equipment loopback, and
loop timing modes. The part is packaged in a 64-pin PQFP with integrated heat spreader for optimum thermal
performance and reduced cost. The VSC8117 provides an integrated solution for ATM physical layers and
SONET/SDH systems applications.
Functional Description
The VSC8117 is designed to provide a SONET/SDH compliant interface between the high speed optical
networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8117
converts 8 bit parallel data at 77.76Mb/s or 19.44Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s
respectively. The device also provides a Facility Loopback function which loops the received high speed data
and clock (optionally recovered on-chip) directly to the high speed transmit outputs. A Clock Multiplier Unit
(CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream
from input reference frequencies of 19.44 or 77.76 MHz. The CMU can be bypassed with the recovered clock in
loop timing mode thus synchronizing the entire part to a single clock. The block diagram on page 2 shows the
major functional blocks associated with the VSC8117.
The receive section provides the serial-to-parallel conversion, converting the 155.52Mb/s or 622.08Mb/s bit
stream to an 8 bit parallel output at 19.44Mb/s or 77.76Mb/s respectively. A Clock Recovery Unit (CRU) is inte-
grated into the receive circuit to recover the high speed clock from the received serial data stream. The receive
section provides an Equipment Loopback function which will loop the low speed transmit data and clock back
through the receive section to the 8 bit parallel data bus and clock outputs. The VSC8117 also provides the
option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a
G52221-0, Rev. 4.1
1/8/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
