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VSC8166 参数 Datasheet PDF下载

VSC8166图片预览
型号: VSC8166
PDF下载: 下载PDF文件 查看货源
内容描述: 2.488 Gb /秒1:16 SONET / SDH多路分配器带有时钟恢复 [2.488 Gbit/sec 1:16 SONET/SDH Demux with Clock Recovery]
分类和应用: 时钟
文件页数/大小: 16 页 / 169 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
Features
• 2.488Gb/s 1:16 Demultiplexer
• Fully Integrated Clock and Data Recovery
• Single 3.3V Supply Operation
• Differential LVPECL Low Speed Interface
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
• Maintains Clock Output in the Absence of
Data
• Loss of Lock, Loss of Signal Indicators
• 128 Pin 14x20x2 mm Enhanced PQFP Pkg.
• 2.3W Max Power Dissipation
General Description
The VSC8166 demultiplexes a 2.488Gbp/s LVPECL serial input datastream (DI+) to 16-bit wide, LVPECL
155Mb/s parallel data outputs (D0:D15+) for SONET/SDH applications. It has an integrated clock and data
recovery unit with an on-chip PLL that internally generates a 2.488GHz clock in phase with the incoming data.
Internal divider circuits are used to take the high-speed clock and generate 155.52MHz (CLK16O+) and
77.76MHz (CLK32O+) LVPECL external output clocks. The incoming data is retimed and demultiplexed to a
16-bit word which is clocked out of the demultiplexer by the 155.52MHz output clock.
Alarm functions support typical telecom system applications. A TTL Loss Of Lock (LOL) indicator can be
externally enabled (LOLEN) to detect when the device goes out of lock, which would most often occur in the
event of a loss of valid data. A TTL No-Reference (NOREF) output indicator flags when the LVPECL Clock
Reference (REFCLK) input to the VSC8166 either is removed, or goes severely out of tolerance. For Loss Of
Signal (LOS) conditions from an Optics Module, the VSC8166 provides a polarity (POL) input to accommo-
date any polarity differences.
Only a single 3.3V power supply is required for device operation and the device is packaged in a thermally
enhanced 128 Pin 14x20x2 mm PQFP Package.
VSC8166 Block DIagram
D0+
D0-
Output Register
1:16 DMUX
DI+
DI-
REFCLK+
REFCLK-
Data
Re-time
Clock
Recovery
Divide
by 16
D15+
D15-
CLK16O+
CLK16O-
POL
LOS
LOLEN
Divide
by 2
CLK32O+
CLK32O-
NOREF
LOL
1
0
G52252-0, Rev. 3.0
11/9/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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