VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC834
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
Programming Interface
The switch core is programmed through a parallel interface circuit that allows random reads or writes to the
program memory array. The program memory array is buffered to allow multiple programming instructions to
be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate.
The program data is composed of two parts: output address and input address. The output address, denoted
by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[4:0],
specifies which input port the switch slice should connect to. The format of the program data is simple binary,
where the binary value maps directly to the switch slice position and/or input port number. For example:
ADDR[5:0] (000100) / DATA[4:0] (00110) would direct output channel Y4 to connect to input channel A6. The
programming state may be verified (read back) by applying the address of the desired output and asserting
RDB. The programming state is unknown at power-on. Additional address space is provided for access to the
monitor registers (See Table 2). The microprocessor interface consists of the following signals. Levels are TTL
(see Table 6).
Table 1: Signal Table
Pin
D[5:0]
A[5:0]
ALE
CSB
WRB
RDB
INTB
I/O
B
I
I
I
I
I
O
Description
Bidirectional data bus to transfer data to/from internal program registers
Address bus to select internal program registers for read-write operations
Address Latch Enable: for use with multiplexed address/data buses. Latches the address bus internally
when low.
Chip Select (Active Low): assert this pin whenever the part is being read or programmed.
Write (Active Low): program data will be transferred to the first level internal registers on the rising
edge of this signal (when CSB is also low).
Read (Active Low): program data from the internal program or monitor registers will be read out on the
data bus when this signal goes low (with CSB also low).
Interrupt (Active Low): this signal is asserted when an LOA condition is found
Configure (Active High): assert this signal to transfer queued program information from the first-level
internal registers to the second-level registers, making the programming take effect. This signal may be
tied high to leave the second-level registers transparent so all programming will take effect
immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a high-
order bit of the address bus
Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not
expected to exceed 3MHz.
CONFIG
I
MONCLK
I
Loss of Activity (LOA) Monitoring
The LOA function consists of an activity monitor on each input channel, connected directly to the pads.
The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying
the address (See Table 2) of the monitor register corresponding to the signal of interest and asserting RDB. Each
monitor register is four bits in length, covering the state of four inputs or outputs. There is one extra one-bit
monitor for each of the 17
th
input and 17
th
output. The state of each monitor is transferred to the register period-
ically on the rising edge of MONCLK, whereupon the activity monitor is clered until more activity is detected.
G52247-0, Rev 4.2
02/09/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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