VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC837
Features
•
•
•
•
•
•
•
68 Input by 68 Output Crosspoint Switch
3.2Gb/s NRZ Data Bandwidth
66MHz Multi-Mode Programming Port
TTL/2.5V CMOS Control I/O (3.3V tolerant)
Programmable On-Chip I/O Termination
Input Signal Activity (ISA) Monitoring Function
Integrated Signal Equalization (ISE) for
Deterministic Jitter Reduction
3.2Gb/s
68x68 Crosspoint Switch
• Single 2.5V Supply
• Differential CML Output Driver
• 11W typ/14W max (low drive mode)
13W typ/16W max (high drive mode)
• Hard and Soft Power-Down for Unused Channels
• High Performance 37.5mm, 480 TBGA Package
General Description
The VSC837 is a monolithic 68x68 asynchronous crosspoint switch, designed to carry broadband data
streams. The non-blocking switch core is programmed through a triple-mode port interface that allows random
access programming of each input/output port. A high degree of signal integrity is maintained throughout the
chip via fully differential signal paths.
The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 68:1
multiplexer that can be programmed to one and only one of its 68 inputs. The signal path is unregistered and
fully asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input.
Each high-speed output is a fully differential switched current driver with switchable on-die terminations
for maximum signal integrity. Data inputs are terminated on die through 100
Ω
resistors between true and com-
plement inputs (see
Input Termination
section for further detail).
A triple-mode programming interface is provided that allows programming commands to be sent as serial
data or one of two forms of parallel data. The input-referred mode (burst mode) allows an input port to be routed
to all outputs in only 4 program cycles. Core programming can be random for each port address, or multiple
program assignments can be queued and issued simultaneously. The programming may be initialized to a
“straight-through” configuration (A0 to Y0, A1 to Y1, etc.) using the INITB pin.
An activity monitor is provided to allow in-system diagnostics. The activity monitor can observe any high-
speed input via an internal 69th multiplexer.
Unused channels may be powered down to allow efficient use of the switch in applications that require only
a subset of the channels. Power-down can be accomplished in hardware, via dedicated power pins for pairs of
input and output channels, or in software by programming individual unused outputs with a disable code.
VSC837 Block Diagram
A0
2
2
Y0
A67
2
2
Y67
µP
control
G52309-0, Rev 3.0
02/16/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
