VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC880
Pin
Name
I/O
Freq
Type
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5MHz
TTL
62.5MHz
TTL
<1MHz
TTL
62.5MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
<1MHz
TTL
High Performance 16x16
Serial Crosspoint Switch
Description
If RESYNEN is HIGH, all links that have a link error
condition will be reinitialized. This will override the internal
control register settings.
If INT is LOW, a receive error has occurred in one of the
links that has it’s output enable (OE) bit set HIGH and
interrupt control register bit set HIGH.
This signal is reserved for future use and should be set LOW
during normal operation.
If this signal is set HIGH, all serial inputs are looped back to
their serial outputs. This will override the internal control
register setting.
CMODE is set HIGH for Cell Mode operation.
This signal is used in ATE testing to measure propagation
delay. It is also used in ATE testing of the BIST logic. Set to
logic LOW in normal operation.
The input signal for measuring propagation delay on the
ATE tester.
The output signal for measuring propagation delay on the
ATE tester. When TESTEN is set LOW, the longer delay
path is enabled.
This is the word clock output.
This is the reference clock and the source of the system wide
word clock period.
This input is set HIGH in test mode, so that the CMU is
bypassed and the REFCLK becomes the bit clock. This
signal is for ATE test only. Set LOW in normal operation.
This is the source of the system wide cell clock. It is
internally synchronized to the REFCLK. In Packet mode, set
this signal HIGH to enable external switch configuration for
BIST.
Global chip reset (active LOW)
When BSTLPBK is set HIGH and TESTEN is LOW, all
serial data output signals are looped back to their serial data
inputs. If BSTLPBK is set HIGH and TESTEN is HIGH,
only ports 0-7 are placed in loopback.
When BSTEN is HIGH, at-speed built-in self testing is
enabled.
The BSTRST signal is set HIGH to reset the PRBS
generator and comparator.
The BSTPASS signal is HIGH if BTSEN is HIGH and the
PRBS comparator detects the correct pattern in built-in self
test mode.
RESYNEN
Resynch Enable
I
INT
MEN
FACLPBK
CMODE
TESTEN
SCANIN
SCANOUT
WCLK
REFCLK
TCLKEN
Interrupt
Reserved
Facility Loop Back
Cell Mode
Scan Test Enable
Scan Data In
Scan Data Out
Word Clock
Reference Clock
Test Clock Enable
O
I
I
I
I
I
O
O
I
I
CCLK
Cell Clock
I
RESET
Reset
Built-in Self Test Loop
Back
Built-in Self Test Enable
Built-in Self Test Reset
Built-in Self Test Pass
I
BSTLPBK
I
BSTEN
BSTRST
BSTPASS
I
I
O
G52191-0, Rev 4.2
01/05/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
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