2.5Gb/s SONET/SDH FEC Encoder and Decoder
Optical
Transport
Networking
VSC9210
Product Brief
Features:
•
Reed Solomon RS(255,241)
Codec
•
Bit Error Rate Improvement
from 10
5
to 10
20
•
Includes Optical Channel
Overhead (OCh-OH) of 10Mb/s
•
Provides Bit Error Rate
Monitoring of FEC Line
•
Processes Data Rates up to
2.654Gb/s and Information
Rates to 2.488Gb/s
•
Provides a Dedicated User
Defined Data Channel at
10.368Mb/s
Product Description
The VSC9210 provides forward error
correction for any data rate and pro-
tocol operating up to 2.5Gb/s using a
block oriented Reed-Solomon For-
ward Error Correction (FEC) algorithm
RS(255,241). The device can be con-
figured as a FEC encoder or a FEC
decoder utilizing two 16-bit differen-
tial PECL I/O ports to interface with
an external high speed multiplexer/
demultiplexer pair. Clock dividers are
provided on chip to facilitate control
of external PLL circuitry.
For the Encoder, the 1:16
Demultiplexer is used to convert the
incoming 2.5Gb/s STS-48 information
to a 16 bit parallel data at 155MHz to
interface with the VSC9210. After the
encoding process, the 16 bit parallel out-
put data from the VSC9210 is obtained
at 165MHz and is converted to a
2.65Gb/s data stream using the 16:1
Multiplexer. In the case of the Decoder
configuration, the Demultiplexer oper-
ates on a 2.65Gb/s data stream while
the Multiplexer provides the 2.5Gb/s
STS-48 information stream. Clock divid-
ers are incorporated within the
VSC9210 to provide control of an ex-
ternal PLL circuit for synthesizing the
necessary reference clock for the Mul-
tiplexer. In the case of the Bypass mode,
the input and output rates are identical
and both the Multiplexer and
Demultiplexer operate at 2.5Gb/s.
Benefits:
•
Device Pin Configured as
Stand-alone Encoder, Decoder,
or Bypass with Cocks Disabled
•
Provides Count of Correctable
0’s and 1’s that are in Error in
Prior Code Word
•
Interfaces Directly with Vitesse
OC-48 Rate Components
www.vitesse.com
Telecom Division
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
