128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
Row Address Entry &
Bank Active
Single Bank Precharge
Precharge All Banks
Column Address Entry
&Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
MNEMONIC
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITE A
READ
READA
REFA
REFS
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
L
CKE
n
X
X
X
X
X
X
X
X
X
H
L
H
H
X
X
/CS
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
/RAS /CAS
X
H
L
L
L
H
H
H
H
L
L
X
H
H
L
X
H
H
H
H
L
L
L
L
L
L
X
H
H
L
/WE BA0,1 A1 1
X
H
H
L
L
L
L
H
H
H
H
X
H
L
L
X
X
V
V
X
V
V
V
V
X
X
X
X
X
L
X
X
V
X
X
V
V
V
V
X
X
X
X
X
L
A1 0
X
X
V
L
H
L
H
L
H
X
X
X
X
X
L
A0-9
X
X
V
X
X
V
V
V
V
X
X
X
X
X
V*1
Self-Refresh Exit
REFSX
L
Burst Terminate
Mode Register Set
TBST
MRS
H
H
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
JULY.2000
Page-6
Rev.2.2
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
