VIS
DQ
inputs
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Column Address
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0~7
0~7
0~7
0~7
0~7
0~7
0~7
0~7
8~15
8~15
8~15
8~15
8~15
8~15
8~15
8~15
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
DQ Planes
Controlled
DQ
Inputs
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Column Address
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DQ Planes
Controlled
16~23
16~23
16~23
16~23
16~23
16~23
16~23
16~23
24~31
24~31
24~31
24~31
24~31
24~31
24~31
24~31
The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following diagram. The DQM and Mask reg-
ister masking operates as for normal Write command, with the exception that the mask information
is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is written only if
a ”0” was registered for the corresponding DQM input, a ”1” was registered for the corresponding DQ
signal, and the corresponding bit in the Mask register is ”1”.
A block write access requires a time period of t
BWC
to execute, so in general, there should be
m NOP cycles, m equals (t
BWC
-t
CK
) /t
CK
rounded up to the next whole number, after the Block Write
command. However, BankActivate or BankPrecharge commands to the other bank are allowed.
When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank, t
BPL
must be met.
Document:
Rev.1
Page 12
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
