VIS
T0
T1
T2
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
T5
T6
T7
T8
T3
T4
CLK
COMMAND
NOP
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
CAS latency = 1
t
CK1
,DQ’s
DIN A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
CAS latency = 2
t
CK2
,DQ’s
CAS latency = 3
t
CK3
,DQ’s
DIN A
0
don’t care
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DIN A
0
don’t care
don’t care
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
Input data must be removed from DQ’ s at least one clock
cycle before the Read data appears on the outputs to avoid
data contention
Input data for the write is masked
Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without auto pre-
charge function should be issued m cycles after the clock edge at which the last data-in element
is registered, where m equals t
WR
/t
CK
rounded up to the next whole number. In addition, the
DQM signals must be used to mask input data, starting with the clock edge following the last
data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll
command is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
NOP
COMMAND
WRITE
Precharge
NOP
NOP
Activate
NOP
ADDRESS
BANK
COLn
t
WR
DIN
n
DIN
n+1
BANK (S)
ROW
DQ
:don’t care
Write to Precharge
When Burst-Read and Single-Write mode is selected , the write burst length is 1 regardless of the
read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8
Block Write command
(RAS = “H” , CAS = “L” , WE = “L”, DSF = “H” , BS =Bank , A8 = “L” , A3-A7 = Column Address, DQ0-DQ31
= Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A single
data value, which was previously loaded in the Color register, is written to the block of eight consecutive
column locations addressed by inputs A3-A7. The information on the DQs which is registered coincident with
the Block Write command is used to mask specific column/byte combinations within the block . The mapping
of the DQ inputs to the column/byte combinations is shown in following table.
Document:
Rev.1
Page 11
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
