欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDI2CG472256V15D2 参数 Datasheet PDF下载

EDI2CG472256V15D2图片预览
型号: EDI2CG472256V15D2
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆字节同步/同步连拍,双DIMM关键 [8 Megabyte Sync/Sync Burst, Dual Key DIMM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 11 页 / 203 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
 浏览型号EDI2CG472256V15D2的Datasheet PDF文件第2页浏览型号EDI2CG472256V15D2的Datasheet PDF文件第3页浏览型号EDI2CG472256V15D2的Datasheet PDF文件第4页浏览型号EDI2CG472256V15D2的Datasheet PDF文件第5页浏览型号EDI2CG472256V15D2的Datasheet PDF文件第6页浏览型号EDI2CG472256V15D2的Datasheet PDF文件第7页浏览型号EDI2CG472256V15D2的Datasheet PDF文件第8页浏览型号EDI2CG472256V15D2的Datasheet PDF文件第9页  
White Electronic Designs
8 Megabyte Sync/Sync Burst, Dual Key DIMM
FEATURES
4x256Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear and Sequential Burst Support via MODE pin
Clock Controlled Registered Module Enable (EM#)
Clock Controlled Registered Bank Enables (E1#, E2#,
E3#, E4#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables (BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally Self-timed Write
Individual Bank Sleep Mode enables (ZZ
1
, ZZ
2
, ZZ
3
, ZZ
4
)
Gold Lead Finish
3.3V +10%, - 5% Operation
Access Speed(s): TKHQV=9, 10, 12, 15ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access Speed
Single Total Array Clock
Multiple Vcc and Gnd
EDI2CG472256V
ADVANCED*
DESCRIPTION
The EDI2CG472256VxxD2 is a Synchronous/Synchronous
Burst SRAM, 84 position Dual Key; Double High DIMM (168
contacts) Module, organized as 4x256Kx72. The Module
contains sixteen (16) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm
TQFP placed on a Multilayer FR4 Substrate. The module
architecture is defined as a Sync/Sync Burst, Flow-
Through, with support for either linear or sequential burst.
This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only
Mode, provides a high performance cost advantage over
BiCMOS aysnchronous device architectures.
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP# / ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well as
an Asynchronous Output enable. This Module has been
defined with full flexibility, which allows individual control
of each of the eight bytes, as well as Quad Words in both
Read and Write Operations.
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com