White Electronic Designs
WRITE CYCLE 2 - E# CONTROLLED
TAVAV
A
TAVEL
E#
TAVEH
TWLEH
W#
TDVEH
D
Q
HIGH Z
TEHDX
DATA VALID
EDI8F81024C
TELEH
TEHAX
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
Note 1: Parameter guaranteed, but not tested.
* Read Cycle Time
Sym
V
CC
I
CCDR
TCDR
TR
Test Conditions
V
CC
= 0.2V
E#
≥
V
CC
-0.2V
V
IN
≥
V
CC
-0.2V
or V
IN
≤
0.2V
V
CC
Min
2
–
–
0
TAVAV*
Typ
–
25
50
–
–
70°C
–
300
450
–
–
Max
85°C
–
400
550
–
–
Unit
V
µA
µA
ns
ns
2V
3V
DATA RETENTION E# CONTROLLED
DATA RETENTION MODE
V
CC
TCDR
4.5V
V
CC
4.5V
TR
E#
E#≥VDD-0.2V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
