White Electronic Designs
512Kx32 SRAM Module.3.3V
FEATURES
DSP Memory Solution
ADSP-21060L (SHARC)
ADSP-21062L (SHARC)
Texas Instruments TMS320LC31
MPC860 (Power Quic)
Fast Access Times: 12, 15, 17, and 20ns
Individual Byte Enables
User configuration organization with Minimal
Additional Logic
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
68 Lead PLCC, No. 99 JEDEC MO-47AE
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum Noise
Immunity
EDI8L32512V
DESCRIPTION
The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM.
The device is available with access times of 12, 15, 17 and
20ns allowing the creation of a no wait state DSP and RISC
microprocessor memory solutions.
The device can be configured as a 512K x 32 and used to
create a single chip external data memory solution for TI's
TMS320LC31 (figure 5), or Analog's SHARC
TM
DSP (figure
6).
The device provides a 56% space savings when compared
to four 512Kx8, 36 pin SOJs. In addition the EDI8K32512V
has only a 10pF load on the data lines vs. 32 pF for four
plastic SOJs.
The device provides a memory upgrade of the EDI8F32256V
(256K x 32) or the EDI8L32128V (128K x 32) (figure 8).
Alternatively, the device's chip enables can configure it as
a 1M x 16. A 1M x 48 program memory array for Analog's
CHARC DSP is created using three devices (figure 7).
If
RISC Memory Solution
Random Access Memory Array
Surface Mount Package
this memory is too deep, two 512K x 24s (EDI8L24512V)
can be used to create a 512K x 48 array or two 128K x
24s (EDI8L24128V) can be used to create a 128K x 48
array.
Note: Soldier Reflow Temperature should not exceed 260°C for 10 seconds.
Single +3.3V (±5%) Supply Operation
FIG. 1
PIN CONFIGURATIONS
DQ16
A18
A17
E3#
E2#
E1#
E0#
NC
V
CC
NC
NC
G#
W#
A16
A15
A14
DQ15
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
A0-A18
E0#-E3#
PIN DESCRIPTION
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
CC
DQ24
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
V
CC
DQ7
DQ6
DQ5
DQ4
V
SS
DQ3
DQ2
DQ1
W#
G#
DQ0-DQ31
V
CC
V
SS
NC
Address Inputs
Chip Enables
(One per Byte)
Master Write Enable
Master Output Enable
Common Data
Input/Output
Power (+3.3V±5%)
Ground
No Connectiona
BLOCK DIAGRAM
A0-18
G#
W#
E0#
E1#
E2#
E3#
1
19
512K x 32
Memory
Array
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October. 2000
Rev. 3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
DQ31
A6
A5
A4
A3
A2
A1
A0
V
CC
A13
A12
A11
A10
A9
A8
A7
DQ0
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
