White Electronic Designs
FIG. 2 FUNCTIONAL BLOCK DIAGRAM
WE
0
#
RAS
0
#
CAS
0
#
WE# RAS# CAS#
V
REF
A
0-12
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
W3E32M72S-XSBX
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to V
CC
and V
CCQ
simultaneously, and
then to V
REF
(and to the system V
TT
). V
TT
must be applied
after V
CCQ
to avoid device latch-up, which may cause
permanent damage to the device. V
REF
can be applied any
time after V
CCQ
but is expected to be nominally coincident
with V
TT
. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after V
CC
is
applied. After CKE passes through V
IH
, it will transition to
an SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the D
LL
, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the D
LL
and to program the operating
parameters. Two-hundred clock cy cles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (t
RFC
must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
pa ram e ters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
V
REF
A
0-12
BA
0-1
CK
0
CK
0
#
CKE
0
CS
0
#
DQML
0
DQMH
0
DQSL
0
DQSH
0
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U0
WE
1
#
RAS
1
#
CAS
1
#
WE# RAS# CAS#
V
REF
A
0-12
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
16
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
31
CK
1
CK
1
#
CKE
1
CS
1
#
DQML
1
DQMH
1
DQSL
1
DQSH
1
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U1
WE
2
#
RAS
2
#
CAS
2
#
WE# RAS# CAS#
V
REF
A
0-12
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
32
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
47
CK
2
#
CK
2
#
CKE
2
CS
2
#
DQML
2
DQMH
2
DQSL
2
DQSH
2
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U2
WE
3
#
RAS
3
#
CAS
3
#
WE# RAS# CAS#
V
REF
A
0-12
CK
3
CK
3
#
CKE
3
CS
3
#
DQML
3
DQMH
3
DQSL
3
DQSH
3
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U3
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
48
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
63
WE
4
#
RAS
4
#
CAS
4
#
WE# RAS# CAS#
V
REF
A
0-12
CK
4
CK
4
#
CKE
4
CS
4
#
DQML
4
DQMH
4
DQSL
4
DQSH
4
BA
0-1
CK
CK#
CKE
CS#
DQML
DQMH
DQSL
DQSH
U4
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
64
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
79
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
