W3E32M72S-XSBX
White Electronic Designs
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
Notes 1-5, 14-17, 33
333Mbs
CL 2.5
266 Mbs CL 2.5
200 CL 2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
Parameter
Symbol
tAC
Min
-0.70
0.45
0.45
7.5
Max
Min
-0.75
0.45
0.45
7.5
Max
+0.75
0.55
0.55
13
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
13
Min
-0.8
0.45
0.45
10
Max
+0.8
0.55
0.55
13
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
µs
µs
ns
ns
tCK
+0.70
0.55
0.55
13
Access window of DQs from CK/CK#
CK high-level width (30)
CK low-level width (30)
Clock cycle time
tCH
tCL
CL = 2.5 (45, 51)
CL = 2 (45, 51)
tCK (2.5)
tCK (2)
tDH
10
13
10
13
13
15
0.45
0.45
1.75
-0.6
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CK/CK#
DQS input high pulse width
0.5
0.6
0.6
2
0.6
tDS
0.5
0.6
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
1.75
-0.75
0.35
0.35
2
+0.6
+0.75
-0.8
0.35
0.35
+0.8
-0.8
0.35
0.35
+0.8
0.35
0.35
DQS input low pulse width
0.45
1.25
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period (34)
0.5
0.6
0.6
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
0.2
tDSH
0.2
0.2
0.2
tCH, tCL
tHP
tCH,tCL
tCH,tCL
tCH,tCL
+0.70
Data-out high-impedance window from CK/CK# (18, 42)
Data-out low-impedance window from CK/CK# (18, 42)
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
tHZ
+0.75
+0.8
+0.8
-0.70
0.75
0.75
0.8
tLZ
-0.75
0.90
0.90
1
-0.8
1.1
-0.8
1.1
tIH
F
tIS
1.1
1.1
F
tIH
1.1
1.1
S
0.8
tIS
1
1.1
1.1
S
12
tMRD
tQH
tQHS
tRAS
15
16
16
tHP - tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
0.55
0.75
1
1
42
15
60
72
15
15
0.9
0.4
12
0.25
0
70,000
ACTIVE to PRECHARGE command (35)
40
20
65
75
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (49)
tRAP
tRC
tRFC
ACTIVE to READ or WRITE delay
tRCD
tRP
PRECHARGE command period
1.1
0.6
DQS read preamble (43)
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
1.1
0.6
1.1
0.6
1.1
0.6
DQS read postamble (43)
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20, 21)
0.4
15
1
0.6
DQS write postamble (19)
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
Write recovery time
Internal WRITE to READ command delay
tWTR
na
tQH - tDQSQ
Data valid output window (25)
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
70.3
35
REFRESH to REFRESH command interval (23) (Commercial & Industrial only)
REFRESH to REFRESH command interval (23) (Military temperature only)*
Average periodic refresh interval (23) (Commercial & Industrial only)
Average periodic refresh interval (23) (Military temperature only)*
Terminating voltage delay to VDD
tREFC
tREFC
tREFI
tREFI
tVTD
70.3
35
70.3
35
70.3
35.15
7.8
7.8
3.8
7.8
3.9
7.8
3.9
3.9
0
0
0
0
75
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tXSNR
tXSRD
75
80
80
200
200
200
200
* Self refresh available in commercial and industrial temperatures only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2006
Rev. 6
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
