White Electronic Designs
GENERAL DESCRIPTION
The W78M32V-XBX is a 256Mb, 3.3 volt-only Page Mode
and Simultaneous Read/Write Flash memory device.
The device offers fast page access times allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip
enable (CS#), write enable (WE#) and output enable (OE#)
controls. Simultaneous Read/Write Operation with Zero
Latency.
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space
into 4 banks, which can be considered to be four separate
memory arrays as far as certain operations are concerned.
The device can improve overall system performance by
allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations
operating at any one time). This releases the system from
waiting for the completion of a program or erase operation,
greatly improving system performance.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
W78M32V-XBX
JEDEC 42.4 single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register contents
serve as inputs to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. The Unlock Bypass mode facilitates
faster programming times by requiring only two write cycles
to program data instead of four. Device erasure occurs by
executing the erase command sequence.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data# Polling)
and DQ6 (toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors to
be erased and reprogrammed without affecting the data
contents of other sectors.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write operations
during power transitions. The hardware sector protection
feature disables both program and erase operations in any
combination of sectors of memory. This can be achieved
in-system or via programming equipment.
The Erase Suspend/Erase Resume
feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If
a read is needed from the SecSi Sector area (One Time
Program area) after an erase suspend, then the user must
use the proper command sequence to enter and exit this
region.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Bank
A
B
C
D
Sectors
16 Mbit (4 Kw x 8 and 32 Kw x 31)
48 Mbit (32 Kw x 96)
48 Mbit (32 Kw x 96)
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Page Mode Features
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
Standard Flash Memory
Features
The device requires a 3.3 volt power supply for both read and
write functions. Internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
