White Electronic Designs
READ
Figure 5 shows Read cycle waveforms. A read cycle begins
with selection address, chip select and output enable. Chip
select is accomplished by placing the CS# line low. Output
enable is done by placing the OE# line low. The memory
WE512K8, WE256K8,
WE128K8-XCX
places the selected data byte on I/O0 through I/O7 after the
access time. The output of the memory is placed in a high
impedance state shortly after either the OE# line or CS# line
is returned to a high level.
FIGURE 5 – READ WAVEFORMS
ADDRESS
CS#
OE#
OUTPUT
NOTE:
OE# may be delayed up to t
ACS
-t
OE
after the falling edge of CS# without impact on t
OE
or by t
ACC
-t
OE
after an address change without impact on t
ACC
.
AC READ CHARACTERISTICS (See Figure 5)
FOR WE512K8-XCX
V
CC
= 5.0V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
Symbol
trc
tacc
tacs
toh
toe
tdf
-150
Min
150
Max
150
150
0
85
70
0
85
70
Min
200
-200
Max
200
200
0
100
70
Min
250
-250
Max
250
250
0
125
70
Min
300
-300
Max
300
300
Unit
ns
ns
ns
ns
ns
ns
FOR WE256K8-XCX and WE128K8-XCX
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
Symbol
trc
tacc
tacs
toh
toe
tdf
-150
Min
150
Max
150
150
0
85
70
0
85
70
Min
200
-200
Max
200
200
Unit
ns
ns
ns
ns
ns
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
