White Electronic Designs
WRITE
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs first. A byte write operation will
automatically continue to completion.
WE32K32-XXX
The WE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
AC Write Characteristics
V
CC
= 5.0V, GND = 0V, -55°C ≤ T
A
≤ +125°C
WRITE CYCLE
Write Cycle Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Write Pulse Width High
Output Enable Set-up Time
Output Enable Hold Time
-80
Symbol
Min
t
WC
t
AS
t
WP
t
CS
t
AH
t
DH
t
CSH
t
DS
t
WPH
t
OES
t
OEH
0
100
0
50
0
0
50
50
10
10
Max
10
0
100
0
50
0
0
50
50
10
10
Min
Max
10
30
150
0
100
10
0
100
50
10
10
Min
Max
10
30
150
0
100
10
0
100
50
10
10
Min
Max
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-90
-120
-150
Unit
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
