WED2DL32512V
512Kx32 Synchronous Pipeline Burst SRAM
FEATURES
s
Fast clock speed: 200, 166, 150 & 133MHz
s
Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
s
Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
s
Single +3.3V power supply (V
DD
)
s
Separate +3.3V or +2.5V isolated output buffer supply (V
DDQ
)
s
Snooze Mode for reduced-power standby
s
Single-cycle deselect
s
Common data inputs and data outputs
s
Individual Byte Write control and Global Write
s
Clock-controlled and registered addresses, data I/Os and control signals
s
Burst control (interleaved or linear burst)
s
Packaging:
• 119-bump BGA package
s
Low capacitive bus loading
PRELIMINARY*
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16
SRAMs into a single BGA package to provide 512K x 32 configura-
tion. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE), burst control input (ADSC) and byte write enables (BW
0-3
).
Asynchronous inputs include the output enable (OE), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. Write cycles
can be from one to four bytes wide, as controlled by the write control
inputs. Burst operation can be initiated with the address status
controller (ADSC) input.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
FIG. 1
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
PIN CONFIGURATION
(TOP VIEW)
2
SA
SA
SA
NC
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
NC
SA
NC
DC
3
SA
SA
SA
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
MODE
SA
DC
4
NC
ADSC
V
DD
NC
CE
OE
NC
NC
V
DD
CLK
NC
BWE
SA1
SA0
V
DD
SA
DC
5
SA
SA
SA
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
SA
DC
6
SA
SA
SA
NC
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
NC
SA
NC
NC
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
BW
c
BW
d
SA
CLK
ADSC
OE
BWE
CE
MODE
ZZ
BW
a
BW
b
BLOCK DIAGRAM
512K x 16
SSRAM
DQ
a
DQ
b
512K x 16
SSRAM
DQ
c
DQ
d
NOTE: DC = Do Not Connect
January 2000 Rev. 0
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
