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WED2ZL361MS38BI 参数 Datasheet PDF下载

WED2ZL361MS38BI图片预览
型号: WED2ZL361MS38BI
PDF下载: 下载PDF文件 查看货源
内容描述: 1Mx36同步管道突发NBL SRAM [1Mx36 Synchronous Pipeline Burst NBL SRAM]
分类和应用: 静态存储器
文件页数/大小: 12 页 / 647 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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White Electronic Designs
1Mx36 Synchronous Pipeline Burst NBL SRAM
FEATURES
Fast clock speed: 250, 225, 200, 166, 150,
133MHz
Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns
Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8,
4.2ns
Separate +2.5V ± 5% power supplies for Core, I/O
(V
CC
, V
CCQ
)
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data
I/Os and control signals
Burst control (interleaved or linear burst)
Packaging:
119-bump BGA package
Low capacitive bus loading
WED2ZL361MS
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an
advanced CMOS process. WEDC’s 32Mb SyncBurst
SRAMs integrate two 1M x 18 SRAMs into a single BGA
package to provide 1M x 36 configuration. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single-clock input (CK). The NBL or No
Bus Latency Memory utilizes all the bandwidth in any
combination of operating cycles. Address, data inputs, and
all control signals except output enable and linear burst
order are synchronized to input clock. Burst order control
must be tied “High or Low.” Asynchronous inputs include the
sleep mode enable (ZZ). Output Enable controls the outputs
at any given time. Write cycles are internally self-timed and
initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation and
provides increased timing flexibility for incoming signals.
NOTE: NBL (No Bus Latency) is equivalent to ZBT™
PIN CONFIGURATION
(TOP VIEW)
4
SA
ADV#
V
CC
NC
CE1#
OE#
SA
WE#
V
CC
CK
NC
CKE#
SA1
SA0
V
CC
SA
NC
1
A
B
C
D
E
F
G
H
J
K
L
V
CCQ
SA
NC
DQc
DQc
V
CCQ
DQc
DQc
V
CCQ
DQd
DQd
2
SA
CE2
SA
DQPc
DQc
DQc
DQc
DQc
V
CC
DQd
DQd
DQd
DQd
DQPd
SA
NC
NC
3
SA
SA
SA
V
SS
V
SS
V
SS
BWc#
V
SS
NC
V
SS
BWd#
V
SS
V
SS
V
SS
LBO#
SA
NC
5
SA
SA
SA
V
SS
V
SS
V
SS
BWb#
V
SS
NC
V
SS
BWa#
V
SS
V
SS
V
SS
NC
SA
NC
6
SA
CE2#
SA
DQPb
DQb
DQb
DQb
DQb
V
CC
DQa
DQa
DQa
DQa
DQPa
SA
NC
NC
7
V
CCQ
NC
NC
DQb
DQb
V
CCQ
DQb
DQb
V
CCQ
DQa
DQa
V
CCQ
DQa
DQa
NC
ZZ
V
CCQ
CK
CKE#
ADV#
LBO#
CE1#
CE2
CE2#
OE#
WE#
ZZ
BLOCK DIAGRAM
BWa#
BWb#
BWc#
BWd#
1M x 18
CK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
CK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
1M x 18
Address Bus
(SA0 - SA19)
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
M
V
CCQ
N
DQd
P
R
T
U
DQd
NC
NC
V
CCQ
DQa - DQd
DQPa - DQPd
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com