White Electronic Designs
Notes
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
CC
, V
CCQ
= +3.3V; = 25°C; pin under test biased at
1.4V. f = 1 MHz, TA
3. I
DD
is dependent on output loading and cycle rates.Specified values are obtained
with mini-mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ ≤ 70°C) is T
A
ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (V
CC
and V
CCQ
must be powered up simultaneously. V
SS
and V
SSQ
must be at same potential.) The
two AUTO REFRESH command wake-ups should be repeated any time the t
REF
refresh requirement is exceeded.
7. AC characteristics assume t
T
= 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a mono-tonic manner.
9. Outputs measured at 1.5V with equivalent load:
WED3DG7264V-D1
PRELIMINARY
Q
50pF
10. t
HZ
defines the time at which the output achieves the open circuit condition; it is not
a reference to V
OH
or V
OL
. The last valid data element will meet t
OH
before going
High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V, with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at V
IL
(MAX) and V
IH
(MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13. I
DD
specifications are tested after the device is properly initialized.
14. Timing actually specified by t
CKS
; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by t
WR
plus t
RP
; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by t
WR
.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The I
DD
current will increase or decrease in a proportional amount by the amount
the frequency is altered for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on t
CK
= 7.5ns for 75/10 and 7.
22. V
IH
overshoot: V
IH
(MAX) = V
CCQ
+ 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. V
IL
under-shoot: V
IL
(MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including t
WR
, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (t
RP
) begins 7.5ns/7ns
after the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27. t
AC
for 75/10/7 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For 75/10, CL = 3, t
CK
= 7.5ns; For 7, CL = 2, t
CK
= 7.5ns
30. CKE is HIGH during refresh command period t
RFC
(MIN) else CKE is LOW. The I
DD6
limit is actually a nominal value and does not result in a fail value.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 4
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
