欢迎访问ic37.com |
会员登录 免费注册
发布采购

WED3EG6418S262D4 参数 Datasheet PDF下载

WED3EG6418S262D4图片预览
型号: WED3EG6418S262D4
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB- 16Mx64 DDR SDRAM UNBUFFERED W / PLL [128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 7 页 / 81 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
 浏览型号WED3EG6418S262D4的Datasheet PDF文件第1页浏览型号WED3EG6418S262D4的Datasheet PDF文件第2页浏览型号WED3EG6418S262D4的Datasheet PDF文件第3页浏览型号WED3EG6418S262D4的Datasheet PDF文件第4页浏览型号WED3EG6418S262D4的Datasheet PDF文件第6页浏览型号WED3EG6418S262D4的Datasheet PDF文件第7页  
WED3EG6418S-D4
FINAL
I
DD
SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, t
A
= 0 to 70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V)
Parameter
Symbol
Conditions
One device bank; Active = Precharge;
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ, DM and DQS inputs changing
once per clock cycle; Address and control
inputs changing once every two cycles.
One device banks; Active-Read-Precharge;
Burst = 2; t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); l
OUT
=0mA; Address and control inputs
changing once per clock cycle.
All device bank idle; Power-down mode;
t
CK
=t
CK
(MIN); CKE=(low)
CS# = High; All device banks idle;
t
CK
=t
CK
(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
V
IN
= V
REF
for DQ, DQS and DM.
One device bank active; Power-down mode;
t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
RC
=t
RAS
(MAX);
t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle
Burst = 2; Reads; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); I
OUT
=0mA
Burst=2; Writes; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
t
RC
=t
RC
(MIN)
CKE £ 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
RC
=t
RC
(MIN);
t
CK
=t
CK
(MIN); Address and control input
change only during Active Read or Write
commands.
DDR333@CL=2.5
Max
DDR266@CL=2, 2.5
Max
DDR200@CL=2
Max
Units
Operating Current
I
DD0
840
760
680
mA
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
I
DD1
1040
960
880
mA
I
DD2P
24
24
24
mA
I
DD2F
200
180
160
mA
I
DD3P
280
280
225
mA
Active Standby Current
I
DD3N
495
440
360
mA
Operating Current
I
DD4R
1280
1140
960
mA
Operating Current
I
DD4W
1216
1040
815
mA
Auto Refresh Current
Self Refresh Current
I
DD5
I
DD6
1520
16
1440
16
1315
16
mA
mA
Operating Current
I
DD7A
2640
2400
1920
mA
* Module I
DD
was calculated on the basis of component I
DD
and can be different measured according to DQ loading cap.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct. 2002
Rev. # 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com