White Electronic Designs
SIGNAL DESCRIPTION
SIGNAL NAME
RESET
D(15-0)
IOWR
IORD
CSEL
IRQ
IOCS16
PDIAG
A(2-0)
CS0
CS1
DASP
DIR
I
I/O
I
I
I
O
O
I/O
I
I
I
I/O
PIN
100
70,62,54,46,38,30,
22,14,10,18,26,34,
42,50,58,66
84
82
98
96
124
118
110,120,122
74
80
116
WED7GxxxIDE36
WED7GxxxIDE33
PRELIMINARY*
IORDY
GND
Vcc
O
102
2,6,128
4,126
DESCRIPTION
HOST RESET. Reset signal from the host that is active on power up.
HOST DATA. These 16 lines carry the data between the controller and the host. The
low 8 lines transfer commands, status and ECC information between the host and the
controller.
I/O WRITE. This strobe pulse is used to clock data or commands on the host data
bus into the controller. The clocking will occur on the negative to positive edge of the
signal (trailing edge).
I/O READ. This is a read strobe generated by the host. This signal gates data or
status on the host bus and strobes the data from the controller into the host on the
low to high transition (trailing edge).
This internally pulled up signal is used to configure this device as a Master or a
Slave. When this pin is grounded by the host, this device is configured as a Master.
When this pin is high (or open), this device is configured as a Slave.
INTERRUPT REQUEST. This is an interrupt request from the controller to the host,
asking for service. The output of this signal is tri-stated when the interrupts are
disabled by the host.
I/O SELECT 16. This open drain output is asserted low by the controller to indicate to
the host the current cycle is a16 bit word data transfer.
PASS DIAGNOSTIC. This bi-directional open drain signal is asserted by the slave
after anExecute Diagnostic command to indicate to the master it has passed its
diagnostics.
HOST ADDRESS. These address lines are used to select the registers within the
controller task file.
HOST CHIP SELECT 0. This is a chip select signal that is used to select the
controller task file.
HOST CHIP SELECT 1. This is a chip select signal that is used to select the control
and diagnostic register.
DISK ACTIVE/SLAVE PRESENT. This open drain output signal is asserted low any
time the drive is active. In a master/slave configuration, this signal is used by the
slave to inform the master a slave is present.
This is an optional signal that is negated when the drive is not ready to respond to a
data transfer request. For the module this signal is not used, the pin is pulled up. As
long as the host obeys PIO mode 0 or 4 timing, the module is guaranteed to respond
properly.
GROUND.
POWER (3.3V – 5V)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2003
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
