WED7GxxxIDE36
WED7GxxxIDE33
White Electronic Designs
PRELIMINARY*
RDY/BSY line becomes ready again, the module may have
correctly written the data, but this is not ensured. Therefore
the data may be corrupted.
POWER BACKUP TIMING
Shown in the following two figures are the differences in
operation between the WED7GxxxIDE33 module, and the
WED7GxxxIDE36 module with Power Failure Protection
Circuit.
Figure 2 shows the protected module. The power is again
lost after the second sector (Sector n+1) is received,
but the internal backup power allows the sector to be
properly written, and the card completes the write sector
operation.
Figure 1 shows how a sector is written to a NAND Flash.
The entire sector is received and then is written at one
time. The RDY/BSY line stays busy until proper writing
of the data is ensured. If power loss occurs before the
FIG. 2 POWER LOSS WITHOUT POWER FAILURE PROTECTION CIRCUIT
Device in Write
Process/Busy
RDY/BSY
Data Written/Device Ready
Sector Write Process
Power Loss
Data Transmitted
Sector n
Sector n+1
Sector n+2
External VCC
Internal VCC
Data Received
Sector n
Sector n+1
Data Written
n
n+1
Possibly Corrupted Sector
Note: Sector Blocks in these diagrams do not represent a difference with size of data written, between the data received and the data written. This represents the
shorter time to write the data than to transmit it.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2003
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
