White Electronic Designs
3. TRUE IDE MODE
WED7PxxxCFA70xxI25
The card can be configured in a True IDE. This card is configured in this mode only when the OE# input signal is asserted
to GND by the host during power on . In this True IDE mode Attribute Registers are not accessible from the host. Only
I/O operation to the task file and data register is allowed. If this card is configured during power on sequence, data
register is accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature Command to put
the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode
Invalid mode
Standby mode
PIO Data register access
Multiword DMA Data register access
Alternate status access
Other task file access
Note: X → L or H
CE2#
L
H
H
H
L
H
CE1#
L
H
L
H
H
L
A0~A2
X
X
0
X
6H
1~7H
DMACK#
X
H
H
L
H
H
DIOR#
X
X
L
L
L
L
DIOW#
X
X
H
H
H
H
D8~D15
High-Z
High-Z
Odd byte
Odd byte
High-Z
High-Z
D0~D7
High-Z
High-Z
even byte
even byte
Status out
Data
True IDE Mode Write I/O Function
Mode
Invalid mode
Standby mode
PIO Data register access
Multiword DMA Data register access
Control register access
Other task file access
Note: X → L or H
CE2#
L
H
H
H
L
H
CE1#
L
H
L
H
H
L
A0~A2
X
X
0
X
6H
1~7H
DMACK#
X
H
H
L
H
H
DIOR#
X
X
H
H
H
H
DIOW#
X
X
L
L
L
L
D8~D15
Don’t care
Don’t care
Odd byte
Odd byte
Don’t care
Don’t care
D0~D7
Don’t care
Don’t care
even byte
even byte
Control in
Data
CARD SYSTEM PERFORMANCE
ITEM
Set up time (Reset to Ready)
Set up time (Power down to Ready)
Data transfer rate to / from host
Sustained read transfer rate
Sustained write transfer rate
Command to DRQ (Sector Re ad at Ready state)
Command to DRQ (Sector Write at Ready state)
Data transfer cycle end to ready (Sector write)
Auto Power down time
Notes:
1. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
PERFORMANCE
250 ms (max.)
5.5 ms (max.)
16.6 M byte / s burst (max.), theoretically
6.5 M byte / s (max.), actually *1
6.0 M byte / s (max.), actually *1
4 ms (max.)
700 ms (max.)
2 ms (typ.), 200 ms (max.)
1.5s (min.), 1.8s (typ.)
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
