WED8L24258V
Asynchronous SRAM, 3.3V, 256Kx24
FEATURES
n
256Kx24 bit CMOS Static
n
Random Access Memory Array
Fast Access Times: 10, 12, and 15ns
Master Output Enable and Write Control
Three Chip Enables for Byte Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
n
Surface Mount Package
119 Lead BGA (JEDEC MO-163), No. 391
Small Footprint, 14mmx22mm
Multiple Ground Pins for Maximum Noise Immunity
n
Single +3.3V (±5%) Supply Operation
n
DSP Memory Solution
Motorola DSP5630x
Analog Devices SHARC
TM
The JEDEC Standard 119 lead BGA provides a 69% space savings
over using six 256Kx4, 300 mil wide SOJs and the BGA package
has a maximum height of 110 mils compared to 148 mils for the SOJ
packages. The BGA package also allows the use of the same
manufacturing and inspection techniques as the Motorola DSP, which
is also in a BGA package.
DESCRIPTION
The WED8L24258VxxBC is a 3.3V, twelve megabit SRAM con-
structed with three 256Kx8 die mounted on a multi-layer laminate
substrate. With 10 to 15ns access times, x24 width and a 3.3V
operating voltage, the WED8L24258V is ideal for creating a single chip
memory solution for the Motorola DSP5630x or a two chip solution
for the Analog Devices SHARC
TM
DSP.
The single or dual chip memory solutions offer improved system
performance by reducing the length of board traces and the number
of board connections compared to using multiple monolithic devices.
FIG. 1
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
I/012
I/013
I/014
I/015
I/016
I/017
NC
I/018
I/019
I/020
I/021
I/022
I/023
NC
NC
PIN CONFIGURATION
PIN SYMBOLS
2
AO
A5
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
A9
A13
3
A1
A6
E2
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A10
A14
4
A2
E0
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
W
G
5
A3
A7
E3
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A11
A15
6
A4
A8
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
A17
A12
A16
7
NC
NC
I/00
I/01
I/02
I/03
I/04
I/05
NC
I/06
I/07
I/08
I/09
I/010
I/011
NC
NC
A
0-17
E
W
G
DQ
0-23
VCC
GND
NC
P
IN
N
AMES
Address Inputs
Chip Enable
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (3.3V ±5%)
Ground
No Connection
BLOCK DIAGRAM
A
0
-A
17
G
W
E
0
E
2
E
3
18
256K x 24
Memory
Array
DQ
0
-
7
DQ
8-15
DQ
16-23
July 2002 Rev. 0A
ECO #15432
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
