WED8L24513V15BC 参数 Datasheet PDF下载

White Electronic Designs

Asynchronous SRAM, 3.3V, 512Kx24

FEATURES

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512Kx24 bit CMOS Static

Random Access Memory Array

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Fast Access Times: 10, 12, and 15ns

Master Output Enable and Write Control

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

119 Lead BGA (JEDEC MO-163), No. 391

Small Footprint, 14mmx22mm

Multiple Ground Pins for Maximum Noise

Immunity

WED8L24513V

DESCRIPTION

The WED8L24513VxxBC is a 3.3V, twelve megabit SRAM

constructed with three 512Kx8 die mounted on a multi-layer

laminate substrate. With 10 to 15ns access times, x24 width

and a 3.3V operating voltage, the WED8L24513V is ideal

for creating a single chip memory solution for the Motorola

DSP5630x (Figure 7) or a two chip solution for the Analog

Devices SHARC

TM

DSP (Figure 8).

The single or dual chip memory solutions offer improved

system performance by reducing the length of board traces

and the number of board connections compared to using

multiple monolithic devices.

The JEDEC Standard 119 lead BGA provides a 61% space

savings over using three 512Kx8, 400 mil wide SOJs and the

BGA package has a maximum height of 110 mils compared

to 148 mils for the SOJ packages.

Surface Mount Package

Single +3.3V (±5%) Supply Operation

DSP Memory Solution

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Motorola DSP5630x

Analog Devices SHARC

TM

PIN CONFIGURATION

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

1

NC

NC

I/012

I/013

I/014

I/015

I/016

I/017

NC

I/018

I/019

I/020

I/021

I/022

I/023

NC

NC

2

AO

A5

NC

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

A18

A9

A13

3

A1

A6

NC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

NC

A10

A14

4

A2

E#

NC

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

NC

W#

G#

5

A3

A7

NC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

NC

A11

A15

6

A4

A8

NC

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

GND

V

CC

A17

A12

A16

7

NC

NC

I/00

I/01

I/02

I/03

I/04

I/05

NC

I/06

I/07

I/08

I/09

I/010

I/011

NC

NC

A0-18

E#

W#

G#

DQ0-23

V

CC

GND

NC

PIN NAMES

Address Inputs

Chip Enable

Master Write Enable

Master Output Enable

Common Data Input/Output

Power (3.3V ±5%)

Ground

No Connection

BLOCK DIAGRAM

A0-A18

G#

W#

E#

19

512K x 24

Memory

Array

DQ0-7

DQ8-15

DQ16-23

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Aug, 2002

Rev. 0A

1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com