WED8L24514V
SRAM, 3.3V,
Asynchronous SRAM, 3.3V, 512Kx24
FEATURES
DESCRIPTION
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512Kx24 bit CMOS Static
Random Access Memory Array
• Fast Access Times: 10, 12, and 15ns
• Master Output Enable and Write Control
• Three Chip Enables for Byte Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
The WED8L24514VxxBC is a 3.3V, twelve megabit SRAM
constructed with three 512Kx8 die mounted on a multi-
layer laminate substrate. With 10 to 15ns access times, x24
width and a 3.3V operating voltage, the WED8L24514V is
ideal for creating a single chip memory solution for the
Motorola DSP5630x or a two chip solution for the Analog
Devices SHARC
TM
DSP.
The single or dual chip memory solutions offer improved
system performance by reducing the length of board
traces and the number of board connections compared
to using multiple monolithic devices.
The JEDEC Standard 119 lead BGA provides a 61%
space savings over using three 512Kx8, 400 mil wide
SOJs and the BGA package has a maximum height of 110
mils compared to 148 mils for the SOJ packages.
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Surface Mount Package
• 119 Lead BGA (JEDEC MO-163), No. 391
• Small Footprint, 14mmx22mm
• Multiple Ground Pins for Maximum Noise Immunity
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Single +3.3V (±5%) Supply Operation
DSP Memory Solution
• Motorola DSP5630x
• Analog Devices SHARC
TM
FIG. 1 PIN CONFIGURATION
P
IN
S
YMBOLS
PIN N
AMES
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
I/0
12
I/0
13
I/0
14
I/0
15
I/0
16
I/0
17
NC
I/0
18
I/0
19
I/0
20
I/0
21
I/0
22
I/0
23
NC
NC
2
A
O
A
5
NC
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
A
18
A
9
A
13
3
A
1
A
6
E
2
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
NC
A
10
A
14
4
A
2
E
0
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
W
G
5
A
3
A
7
E
3
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
NC
A
11
A
15
6
A
4
A
8
NC
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
A
17
A
12
A
16
7
NC
NC
I/0
0
I/0
1
I/0
2
I/0
3
I/0
4
I/0
5
NC
I/0
6
I/0
7
I/0
8
I/0
9
I/0
10
I/0
11
NC
NC
A
0-18
E
W
G
DQ
0-23
V
CC
GND
NC
Address Inputs
Chip Enable
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (3.3V ±5%)
Ground
No Connection
BLOCK DIAGRAM
A
0
-A
18
G
W
E
0
E
2
E
3
19
512K x 24
Memory
Array
DQ
0
-
7
DQ
8-15
DQ
16-23
September 2001 Rev. 2
ECO #14670
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
