White Electronic Designs
(Unit = number of clock)
t
RAS
50ns
6
5
4
t
RP
20ns
3
2
2
Frequency
125MHz (8.0ns)
100MHz (10.0ns)
83MHz (12.0ns)
CAS
Latency
3
3
2
t
RC
70ns
9
7
6
t
RRD
20ns
2
2
2
t
RCD
20ns
3
2
2
t
CCD
10ns
1
1
1
WED9LC6816V
Clock Frequency and Latency Parameters - 125MHz SDRAM
t
CDL
10ns
1
1
1
t
RDL
10ns
1
1
1
Clock Frequency and Latency Parameters - 100MHz SDRAM
(Unit = number of clock)
t
RAS
50ns
5
5
t
RP
20ns
2
2
Frequency
100MHz (12.0ns)
83MHz (12.0ns)
CAS
Latency
3
2
t
RC
70ns
7
6
t
RRD
20ns
2
2
t
RCD
20ns
2
2
t
CCD
10ns
1
1
t
CDL
10ns
1
1
t
RDL
10ns
1
Refresh Cycle Parameters
Parameter
Refresh Period (1,2)
Symbol
t
REF
Min
—
-10
Max
64
Min
—
-12
Max
64
Units
ms
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to
"wake-up" the device.
SDRAM Command Truth Table
SDA
10
Function
Mode Register Set
Auto Refresh (CBR)
Precharge
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto Precharge
Burst Termination
No Operation
Device Deselect
Data Write/Output Disable
Data Mask/Output Disable
Single Bank
Precharge all Banks
SDCE#
L
L
L
L
L
L
L
L
L
L
L
H
X
X
SDRAS#
L
L
L
L
L
H
H
H
H
H
H
X
X
X
SDCAS#
L
L
H
H
H
L
L
L
L
H
H
X
X
X
SDWE #
L
H
L
L
H
L
L
L
H
L
H
X
X
X
BWE#
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
BA
X
BA
BA
BA
BA
BA
X
X
X
X
X
A
12
, A
13
A
11-0
X
L
H
Row Address
L
H
L
H
X
X
X
X
X
4
4
2
2
2
2
2
3
2
Notes
OP CODE
NOTES:
1. All of the SDRAM operations are defined by states of SDCE#, SDWE#, SDRAS#, SDCAS#, and BWE
0-3
# at the positive rising edge of the clock.
2. Bank Select (BA), A12 (BA0) and A13 (BA1) select between different banks.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE# has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE# goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. BWE# also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is
prohibited (zero clock latency).
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
