White Electronic Designs
16Mx64 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 64
• User configurable as 2 x 16M x 32 and 4 x 16M
x 16
Weight: WEDPN16M64V-XB2X - 2.0 grams typical
WEDPN16M64V-XB2X
GENERAL DESCRIPTION
The 128MByte (1Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 67,108,864-bit banks is organized as 8,192 rows
by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst
ori ent ed; accesses start at a selected location and
continue for a pro grammed number of locations in
a programmedsequence. Accesses begin with the
reg is tra tion of an ACTIVE com mand, which is then
followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-12 select the row). The address bits
registered coincident with the READ or WRITE command
are used to select the starting column location for the
burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 1Gb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
BENEFITS
58% SPACE SAVINGS
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 64 density
(W332M64V-XBX)
* This product is subject to change without notice.
Discrete Approach
ACTUAL SIZE
21
WEDPN16M64V-XB2X
21
S
A
V
I
N
G
S
58%
Area
January 2005
Rev. 1
4 x 265mm
2
= 1060mm
2
1
441mm
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
